Alin-Constantin Florea Email and Phone Number

Responsibilities:Manage the Design and Simulation activities within the Packaging DepartmentPackage Roadmap Simulation Services RoadmapImprove PLOC templates for 2.5D, Flip-Chip and Wirebond type packages Training within department, but also to other departmentsBesides managing activities I also continue to have engineering activities and perform package selection, IO ring planning, package design/simulation and release to manufacturing for complex devices, to balance workload within department

Package selection, design, simulation and released successfully to manufacturing.Worked on various projects that had many challenges like: *96 SerDes channels running at 14Gbps combined with high-power computing (200W) *Dual I/O Ring with 128 SerDes channels running at 6.25Gbps in 5-2-5 build-up package along with a 64bit DDR2 interface *512 bit DDR3 at 2133Mbps along with a 20GHz DAC interface *Hybrid package with Wirebond DRAM die placed on top of a flip-chip ASIC with very small form factor *Wirebond die planned so it can be assembled in a TFBGA, DR-QFN and QFN without any changes to the die pad layout *4 channel SerDes running at 14GHz in a Wirebond package

Developed skills for I/O ring planning, package design and simulation.Worked on wirebond and flip-chip packages