Ranging between hardware design, design verification and low-latency software. Having a fantastic time so far!

Hired principally to do design verification on the third-generation Anton chip. Initially concentrated on a new mathematical engine called the bond calculator, which was specialized to calculate forces on bonded sets of atoms. Moved on to the edge tile, which involved tracking complex data flows across many tiles of many chips. Created a parameterizable verification environment that was able to simulate different tiles at different levels of abstraction, particularly in order to verify network-wide fence capabilities. Created both functional and formal testbenches and a tool to share constraints between them. Successfully implemented formal testbenches to hit some hard-to-reach cases.When there was no chip to verify, was tasked initially to use a machine learning model to perform protein-ligand docking at reasonable speed with high accuracy. It turns out that machine learning models for molecular force fields are remarkably unsuited to standard Nvidia AI chips.Created a new FPGA-based engine as a result, based on a systolic array, that appears able to execute models 4-5 times more quickly than Nvidia chips. Wrote everything from a PyTorch compilation and parameterization tool, to the software that turns a graph of nodes into information to feed the systolic array, to the systolic array design in SystemVerilog, to the FPGA layout and physical design constraints. Also included automatic regression testing and highly parameterized build scripts that are able to build the design on many different Xilinx FPGAs.

Hired as a software engineer but seconded to verification and found a useful niche.Responsible, initially jointly but later solely, for the verification of the memory unit in the NFP3200 network processor. This is the largest unit in the chip, consisting of both caches and advanced engines that perform arithmetic, CAM and queuing operations inside the memory unit. This work included tests, stimuli, monitors and scoreboards and was performed mostly in SystemVerilog using OVM. Also ported existing C-based tests into a VPI environment to run with the Verilog.Developed a regression framework to validate and publish work in the source tree, as well as running continuous randomized regression.Currently working as acting verification lead, and creating an innovative strategy for verification, seeking to save the company money overall by using fewer licenses for EDA tools and putting some of that money into enhancing some key internal tools in order to enable substantial amounts of design verification using open-source tools.In addition, now managing IT for the Massachusetts office, including a 200-core server farm.

As part of the fabric software team, created drivers for the BM9600 fabric processor, including setup and ongoing configuration.Implemented a hybrid mode of operation for the QE2000 queuing engine in order to achieve hierarchical traffic shaping via an internal loopback.Updated many of the test harnesses for the Broadcom SBX line of chips in order to make them compatible with the Broadcom SDK (in addition to the old Sandburst SDK) and with the BM9600 fabric processor.Responsible for drivers for many parts of the next-generation queuing engine.

Responsible for the Ingress Packet Processor, which is highly-optimized code running on two of the many CPUs in the TILE processor, and provides first-line classification at 10 Gbps of incoming packets, including flow identification, header checksums, packet buffer management, and control of the DMA engines in the Ethernet interface. This work also includes a Linux driver and significant work both in a management library in user space and in the Tilera hypervisor.Developed techniques for code optimization and management of multiple memory controllers to maximize data throughput.Added 10 Gbps interfaces and debugging capabilities to the TILE simulator.Designed and wrote the initial boot code for the TILE processor.Contributed to the architecture and design of the TILE processor, including revolutionary re-use of existing instructions and techniques to apply to other uses.Ported various GNU tools to the TILE architecture, including gdb.

Responsible for all the networking code in SavaJe OS, the Java-based operating system for cellphones. Implemented multiple changes to the browser framework, substantial enhancements to the networking implementation (including adding asynchronous select-based sockets), and fixed a large quantity of outstanding bugs.Maintained and greatly improved the phone emulator running on Linux.Implemented the framework to allow streaming video on the phone, using the PacketVideo codec library.

Developed OS services as team leader, including management of processor-to-host interaction, development of new services for the processor's table lookup unit, coordination of services required to allow Tornado for Managed Switches to run on the processor, and PCI analysis and debugging across multiple bridges.Implemented software for a new hardware algorithm for longest-prefix match table lookup (for IP routing and the like) and designed technologies to extend this to access control lists.Assisted in the porting of the C-Port driver to Linux, running on a Motorola MCP750 board.Investigated and resolved several bugs in performance-critical datacom applications for major customers, including those other engineers were unable to get a handle on.

C-Port was subsumed into Motorola in 2003, and then spun off as part of Freescale Semiconductor in 2004.In addition to responsibilities otherwise outlined under C-Port: Created SystemC performance models for Freescale’s new RapidIO switch, and led development of software drivers for it.Represented Motorola/Freescale to the Network Processing Forum and to the RapidIO Trade Association, and contributed ideas and technology for industry use.Made substantial contributions to the architecture and design of Motorola's next-generation network processor, including hardware scheduling concepts, and designed the core of its software kernel.

Led a team porting the NetPlane Frame Relay/ATM interworking software to a new platform. This involved understanding of the NetPlane interworking and Frame Relay software, along with VxWorks and the client’s environment, along with detailed modifications to each of the above, including new CLI commands, integration with the customer’s SNMP implementation and of course the dataplane software.Led a team in a $2m contract to create from scratch a lightweight operating system for a new network processor chip, including symmetric and asymmetric multiprocessor components. As part of the project, created a SPARC simulator and debugger, as well as a scheduler, interrupt manager, semaphores and message queues.

Initially employed to design and implement "GlobalPulse", a software modem for GSM mobile phones. Created a modular design, and implemented in Windows 95 and Windows CE. Access to the GlobalPulse technology was a major factor in TDK's purchase of Grey Cell Systems in 1997. It is my understanding that Samsung cellphones are now also powered by the GlobalPulse technology.Designed and implemented microcontroller solutions to fit in the cable between the PC/PDA and phone, in order to perform protocol conversion for those mobile phones whose interfaces were significantly different from RS232, and to provide some physical security for the software (as a dongle). These were implemented on PIC and Atmel AVR controllers.

Responsible jointly with one other for all the code on the "Brown's Box", a secure remote-access server for PC dial-in to IBM mainframes running on a 68000 processor. On addition of Ethernet and Token Ring interfaces to the Box, created the IPX and TCP/IP routers, writing complete protocol stacks from scratch, including PPP, Telnet and a sockets-like interface. Ported the PC dial-in software to Unix. Greatly improved the software engineering of the Box code.