Alberto Magnani Email & Phone Number

Palo Alto, Ca, Us

Serve as expert advising on all aspects of cameras for the commercial PC market.• Drove future camera features including depth sensing, machine learning algorithms, etc.• Innovated by IP creation (12 disclosures) and work with new internal innovations group, LightSpeedLabs.• Mentored and educated within and outside of PS Intelligent Collaboration Architecture group.

Shenzhen, Guangdong, Cn

Engaged on development of Goodix’s first 48Mpixel CMOS Image Sensor for mobile cell phone market.• Provided guidance and direction to design and research engineers on all aspects of sensor design.• Developed innovative solutions and drove patents (2 granted).• Educated and presented core R&D work to top-notch engineering team new to image sensors.

Built and delivered world-class, low-noise and high-sensitivity image sensors. Managed team of analog design, layout engineers, and the pixel design group.• Developed technology roadmaps, future direction, advanced R&D, IP development and patents.• Filed and responded to office actions on twelve patents (all 12 granted as of 2022); drove the group to disclose dozens more.• Drove the 4k Cinema/240fps sensor from definition to tape-out in three quarters, as both the project and people manager, solidifying BAE’s position in the professional video market.• Drove and developed the winning proposal and Program Technical Lead for Low Light Level Night Vision camera for Microsoft’s IVAS (Integrated Visual Augmentation System) for the US Army.• 2019 Business Leader Award winner: Photon Counting Image Sensor.• 2018 Business Leader Award winner: IP Powerhouse.

A California corporation which I started to run my various consulting work through (See below for past contract details.)

Consulted for QuickSilver Technology, Inc. - Specified, designed, synthesized, and tested several versions of an IO controller for a specialized dataflow multiprocessor.

Image Signal Processing pipeline development for a new, thin-film based CMOS sensor. Designed various ASIC modules. Involved in bring-up and debug of ASIC. Developing code for Xilinx FPGA demonstration board. Managed the Digital and Analog design teams.

Responsible for the design of infrared camera systems. Duties included both hardware - Verilog design, coding, and synthesis, and software - coding for an embedded Power PC processor. Worked with existing high frame-rate pipeline which included blob finding and blob analysis, and proposed a new pipeline structure for lower frame-rate, passive marker face recognition.

Start up company focused on commercial building energy conservation

Boise, Idaho, Us

Worked on Image Signal Processing Chips and Camera SOC strategy. Responsible for new algorithm development for the next generation CMOS imaging sensor of Micron’s Systems-On-a-Chip complete cameras line of products. Led a small group to help verify an ASIC falling behind schedule. Conducted basic research on image processing on CMOS Bayer sensors – in particular, studied demosaicking and color science. Managed over thirty engineers with five senior managers.

Us

Functional Manager of the ASIC and Logic Design Group of 12 engineers. Project Lead for the Packet Processor Module (PPM) Project, which contained four large FPGA’s (Ingress Traffic Manager, Egress Traffic Manager, Egress Scheduler, and Modification Engine) and 16 engineers. Brought up the FPGA proof-of-concept card and demonstrated the first level of the system’s functionality, consisting of an ATM cell aggregation function. Provided backup support to a very capable team of three ASIC designers on the Backplane ASIC, a state-of-the-art switch chip providing TDM and packet capabilities with 3.125 Gbps serdes.

Us

Responsible for the architecture, design and development of a switch fabric interface chip, which formatted and buffered both TDM and data flows into an MPLS system.

Two contracts during this time:3Com, Inc.Assisted with all aspects of ASIC development on a next-generation, high-volume NIC card. Assumed responsibility for legacy code, short-term project management, Xilinx, FPGA emulator board development. Cisco Systems, Inc.Designed and synthesized ASICs for various Ethernet switching products.

Designed ASICs for shared memory multi-processor systems. Developed top-level specifications, architecture, cache coherency protocol, and design.

Analyzed back end timing and worked with SiArc to produce the Verite 1000 3D Graphics Accelerator chip. Architected, designed, and implemented a 230 MHz RAMDAC and clock system for the Verite 2000 family. Responsible for resynthesizing major portions of the 2000 on a skeleton crew style cost reduction, through place and route.

Client: Amberwave Systems, Inc.Wrote approximately 2000 lines of custom microcode for the micro-engine of Amberwave’s first switched Ethernet box. Also provided suggestions for updating their micro-engine to optimize some of the microcode.

Palo Alto, Ca, Us

Architected, designed, and implemented a highly parallel, programmable and concurrent, high bandwidth/low latency memory controller for the Sun Ultra 2 workstation in Verilog. Coded approximately 11,500 lines in 11 days, which synthesized to approximately 35,000 gates.

Developed and architected a 64 GB memory system based on packetized data transfers for a 16 processor, mainframe-class, open system MIMD machine. Generated the technical specification and led the design team. Performed detailed design of the Memory Bank Controller ASIC sized in excess of 100,000 gates and 150K bits of embedded RAM. Assembled and managed a team of six.

Friedrichshafen, Baden-Württemberg, De

Projects included design and development of a floating-point complex butterfly multiplier-accumulator CMOS ASIC, a flight qualified R3000 interface board using Actel FPGAs, a custom processor board for a classified flight system, and a custom I/O interface board to the PC/AT bus, which included several Xilinx FPGAs.

Bsee, Computer Architecture And Vlsi Design

Msee, Digital Signal Processing

Vision And Autonomous Systems Center