Alon Hemo Email & Phone Number

Haifa, Il

Leading R&D and Product Engineering global organization, responsible to deliver cutting edge enterprise software products, including Verisium™, Perspec™, vManager™, Jasper™ Applications, System VIP's, Specman® and Formal VIP’s, used by top fortune companies. Initiated and leading Verisium™, Cadence's AI-Driven Verification Platform, including a suite of innovative applications leveraging big data and generative AI to optimize verification productivity and efficiency.

Haifa Area, Israel

Leading Intel's central R&D org (300+ engineers in Israel, USA, India, Malaysia)) that develops and delivers innovative end-to-end SW CAD tools, collaterals and methodologies for Architecture, Power/Performance and RTL Design and Verification. Enabling and serving dozens of top notch design programs (IoT, AI, Client, Servers and Data Center) and ~10K engineers. Led development of complex multi-module and large scale SW applications (Simulators, Compilers, Stimulus Generator, VIP,..) using cutting edge technologies like Constraint Solving, SAT and ML. In charge of sourcing Electronic Design Automation (EDA) industry solutions and fostering academia research. Israel site-manager for the division, responsible for employees’ engagement and commitment, hiring and retaining top talents, and connect it to Israel site strategy. Staff member of Intel Israel Development Center Management.

Responsible for delivering holistic end-to-end system level verification solutions for Intel product development. Oversees the work of 90 engineers and researchers in Israel, USA and India. Cover a large spectrum of customers including Architecture, pre/post-silicon Validation, Firmware & Manufacturing. Provides tools and flows by partnering with external vendors in EDA eco-system and differentiating with in-house solutions for Intel competitive advantage. Accountable to drive convergence and standardization in corporate level. Created and manages multi-stakeholders networks.

Head and establisher of Intel’s Center-of-Excellence for Intel-Architecture verification solutions. Responsible to enable verification of Atom™ and Core™ by delivering holistic verification env including Architecture Simulation, Test Generation, Architectural Coverage and FW. Formed and managed a global team of 45 engineers (Israel, California and Oregon). • Responsible to deliver solutions that cover a large spectrum of customers including Architecture, pre/post-silicon Validation, Firmware & Manufacturing. • Team serves dozens of active projects (devices, client, servers and HPC) and thousands of engineers in 7 development centers worldwide. • Accountable to drive convergence and standardization in corporate level. • Created and manages multi-stakeholders networks ; established cross site relationships and collaborations ; EDA vendors management

Managed an R&D group (~20 people) responsible for Test Generation solutions delivery for Intel CPU and SOC projects. The solutions include end-to-end SW CAD tools, validation collaterals and methodology. Large scale SW. Drove SW performance breakthrough for emulation needs, using algorithms for Constraint Solving decomposition.Drove significant optimizations and convergence of the solution across Intel products, enabling sharing and reuse between pre-silicon validation, post-silicon validation and high-volume-manufacturing teams. The team served hundreds of validation engineers in 6 development centers worldwide and was responsible for Intel’s central converged test content database.

Managed a diverse SW/HW team (~10 people) in the CPU design automation team. Responsible for tools, flows and methodologies in logic design including RTL-to-Schematics verification and gate level simulation. Execution of global quality flows towards products tape-in and crises management under pressure and tight schedule. Piloting EDA vendor capabilities & negotiating delivery. Lead org level horizontal processes.

Technical lead of innovative CAD tool starting from concept to product: requirements, system architecture, project structuring, developers’ tasks planning, implementation, deadlines, QA and product integration. Outstanding delivery in tight schedule and high quality. Won best paper presented in the prestigious “Design and Test Technology Conference” .

Developed a leading edge formal verification CAD tool targeted for sequential (non state-matching) RTL-to-Schematics and RTL-to-RTL formal verification. Experienced all the range of product development tasks including complex algorithms development, integration of SAT mathematical engines, performance tuning, integration and technical support for customers. Responsible for the integration and releases of a large scale SW Tool (~8 developers) used by over 500 design engineers from 7 active CPU projects worldwide.

Master Of Business Administration (M.B.A.), Cum Laude

Bachelor’S Degree, Computer Science, Summa Cum Laude (Gpa 92)