Low Power Lead-Develop and define low power GPU strategy across business units (eg: consumer, workstation, server). Involved from pre-silicon studies to product definitions to bringup/validation/MP. -Creating and driving HW bringup plans for low power features. -Lead deep technical cross-functional debug efforts for major low power silicon blockers using understanding of GPU micro architecture and system level interactions.-Ownership of ROI studies on new features across various defined use cases. Internalize marketing needs to actionable engineering targets. -Developed process to ensure Nvidia products meet various and complex idle power compliance requirements. -Interface with MLPerf organization to help develop methodologies. -Ownership of HW boot sequencing and timing Chip Bringup Lead-Bring-up and validation of NVIDIA's graphics chips using knowledge of graphics architecture, laboratory methodologies, experimentation and measurement techniques.-Characterize, optimize and define the performance and power post silicon. Worked on complex binning methodologies to account for PVT variability. -Detailed evaluation of new features and identifying validation requirements and risks. -Define performance state PORs based on marketing needs and characterization data.-Provide input to design reviews of new products to understand the product before prototypes are built and provide feedback to chip and board designers.-Produce cost/benefit analysis of new features to identify both marketing demand and resource requirements for a successful product integration.-Drive cross functional debug from end to end. Efforts include isolation, root cause, impact analysis, risk assessment, and suggesting/evaluating fixes.-Debug issues related to: di/dt, noise, clocking architecture, power, SW, DVFS, system level interactions (RP/PCH, CPU, GPU, OS, SW, FW), boundary crossings, and more.

• Schematic-Design/Testing/Layout of DC Constant Power circuit that used a variable input voltage as its source (required to draw constant 100uW from decreasing input voltage supply).o Found optimal parts including: DC references, OPAMPs, power sense IC, FETs, and analog multipliers for circuit build-up, and worked with vendors to get parts.o Output power error ranged from 0.4-4.3% error over an input voltage range from 0.8 – 5.0 volts• Design of a high-performance, low-noise stereo microphone power amplifier o Required to drive low impedance headphones, -3dB at 30Hz for 20Ω loads with up to 40dB of gaino Worked with layout specialist to ensure noise was kept to minimumo Design practices include: equalizing Left/Right channels line impedances; equalizing amplifiers to common star-ground distance; ensured proper return ground current path by combining star-ground design with a ground plane.• Schematic-Design/Testing/Lay-out of a DC voltage sense LED circuit with quick turn around (< few days).• Took apart a competitor product and identified key components in the system. Identified connections between components and described a high-level signal flow chart. • Eye diagrams and accessory quality comparisons including DCR and RF immunity• Worked on various projects at the same time with proficiency while meeting deadlines (up to 8 projects).

-First point of contact for UW students to ask questions about opportunities at RIM.-Gave presentations regarding RIM recruiting and the application process.-Held information session booths

• Independent Schematic design and PCB board layout Project (Test platform)o Designed 2-layer PCB board used for testing I2C devices using Protel 99 SE -Designed custom footprints and custom schematic symbols.o Worked with vendors and suppliers to order components to populate board. Created Gerber/Drill files to prototype board through vendor.o Gained exposure to I2C communications and timing diagrams.o Soldered components to board. Footprints varied from 0402, SOT-223 to TO-263.• Worked to design new implementation of Force Sensor resistors (FSRs)o Tested linearity characteristics of force vs. resistanceo Designed and compared circuits to optimize linearity in region of interest. -Compared configurations which made use of BJT current mirror, FET current mirror, and OPAMP.-Compared hand analysis calculations, simulated results (SIMetrix), and real results with circuits on SMD prototype board. -Worked with vendors to obtain necessary parts.• Independently managed and completed qualification of vendor parts.• Performed failure analysis on test boardso Unexpected current readings during qualification. Root cause found to be MLCC cracking, leading to a reduction in the insulation resistanceo Communication errors. Root cause found to be flux remover liquefying in environmental tests leading to non-conductance in connector.o Part failures. Validated through diode/continuity tests.

• Verified efficiency, voltage, and temperature improvement of design change.• Participated in FPGA verification flowo Wrote System Verilog macro define files for simulation environmento Resolved failing simulation test cases• Independent Hardware Verification projecto Developed Expect/TCL scripts for FPGA lab testso Developed FPGA lab test cases based on FPGA verification plano Wrote instructional document and gave presentation on use/benefits of scripts• Tested power supplies to ensure they meet hardware specs.• Used spectrometer to ensure output frequency met expected values.• Automated calculation of output frequency of a system • Used Labview to simulate environment.

Completed some Hardware Verification for various parts. This included power, high speed signal integrity, and some EM. Also debugged problems involving rise/fall times, noise, double clocking, grounding. Worked with oscilloscopes, schematics (paper and Mentor Graphics), and soldering irons. Completed high level tests including functional tests, thermal runs and traffic tests. Verified integrity of fiber optics and associated optical ports. Worked with ball lens and no ball lens fibers. Performed datasheet compares to compare obsolescent parts to available parts to ensure compatibility. Compatibility parameters include (but not limited to) timing, frequency, power and temperature.

Completed and optimized an automated procedure for calculating TL9000 metrics. Metrics include ERI, YRR, LTR, NYR, and partial NPR Developed a CSV creator which used TL9000 information and normalized the data into a CSV

As an Access Database Administrator I (Facilities Registration Database and Market Entry Administration Tool): -Created macros to increase functionality -Enhanced entire database to create an updated, more usable, version Gained a better understanding of the Ontario power grid and market.

• Assisted in developing Distribution Change Control System -Overall process to be followed when a change or modification to an asset has been made Enhanced the FAO program (Fault Adjusted Operation Tool for Breakers) -The FAO allowed Hydro One Networks to conduct operation based maintenance.