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Designing and architecting next-generation Amazon consumer electronics products. Focus areas include mobile phones, machine learning, object recognition, algorithms, signal processing, wireless communications, and hardware accelerators.

Founded Samplify Systems, a venture-backed high-speed compression start-up. Named on 50+ granted Samplify patents. Developed the real-time compression technology, wrote compress/decompress software in C, managed the development of the FPGA hardware prototype, raised a $300k seed round from Charles River Ventures, and attracted a world-class engineering, sales, and marketing team to bring the Samplify vision to market. Raised $23M from Charles River Ventures, Formative Ventures, IDT, and Schlumberger. Visited 50+ customers in US, Europe, and Asia, selling benefits of real-time compression for medical imaging (CT, ultrasound, MRI), seismic (wireline, RTM), wireless (CPRI, LTE, remote radio heads, WiMax), and data conveter (A/D, D/A) applications. Active in recruiting and hiring talented staff of 18+ employees. Quarterly Technical Advisory Board (Stanford, Xilinx, and Graychip/TI members). Awards:Frost & Sullivan Global Systems Product Differentiation Award (2009)EE Times “Innovator of the Year” ACE Award Finalist (2009)EDN Innovations Award for SAM1600 (ADC / DAC category) (2009)EDN Magazine “Hot 100 Products” for SAM1600 16-chan, 65 Msps A/D (2009)Elec Design "Best Medical Technology" Award for AutoFocus Ultrasound Beamforming (2010)Electronic Products “Product of the Year” for SAM1600 16-chan, 65 Msps A/D (2008)

I manage a group of 15 engineers that develop TI's line of digital up- and downconverters. This group includes the principals of the former start-up called Graychip. I am also responsible for the design, specs, and roll-out of the GC1115 crest factor reduction processor. In my present role, I specify many of the new products that TI Palo Alto develops for Wireless Infrastructure (base stations), and then manage the development, fabrication, testing, and market release of these products.

Responsible for architectural definition, specification, management, design, test, production, and market development for TI's wireless infrastructure radio products (formerly the start-up called Graychip). Project manager and lead systems engineer for the GC1115 crest factor reduction (CFR) processor. Gave many customer presentations of GC1115 performance results. Coordinated with DMOS5 (Dallas) fab during first article development. Responsible for chip bring-up in the lab (EVM). Coordinated GC1115 release to production.

Managed a group of five applications engineers that supported Morphics' customer base in Europe and Asia. Gave technical presentations to customers to explain Morphics' reconfigurable 3G baseband processors. Coordinated engineering and marketing tasks to reflect customer requirements. Wrote data sheets and application notes describing many aspects of the 3G (UMTS) air interface standard, and how that standard was implemented in Morphics' CBME processor.

Responsible for overall systems and software engineering of the Command Audio/RCA CA1000, the world’s first audio-on-demand receiver. Designed and developed all DSP software to receive a 19 kbps data stream using FM subcarriers, GMSK demodulation, Viterbi soft decision decoding, interleavers, and Reed-Solomon decoding. The CA data stream contains compressed speech (2.4 kbps AMBE) and audio (16 kbps Dolby AC-3) stored in NAND flash memory for subsequent, listener-directed playback. DSP code developed in C (50%) and TMS320C52 assembly. Wrote specification for and managed the development of an 80k-gate Viterbi ASIC. Wrote numerous specifications that documented the high-level software and systems architecture of the CA wireless delivery protocols. Managed various DSP software consultants and third parties. Actively expanded CA’s intellectual property (six patent applications to USPTO).

Manage a group of DSP engineers for Spectrum Wireless, a start-up building a PCS1900 wireless base station. Responsible for the DSP hardware & software architecture, functional partitioning, interface specifications, real-time control software specs, DSP test and integration plans, system simulations, task descriptions, and cost/schedule planning. Used TI TMS320C54x + Code Composer, Alta Group's GSM Verification Environment, MATLAB; VxWorks on '486; Xilinx 4000 series FPGAs.

VP Engineering (Apr 93 - May 95)Managed a 14-person engineering department that develops Dyaxis II, a Macintosh-controlled digital audio workstation used for audio post-production. Coordinated SW/HW development plans, manage consultants, develop release features with marketing & bug fixes with software QA, and transition engineering projects to manufacturing. Technical liaison with sister company in France (Studer SA) and parent company (Studer AG) in Switzerland. Ported a lossless audio compression algorithm to SEC's 4x-parallel, 56002 DSP board.Senior DSP Engineer (Aug 90 - Mar 93)Principal DSP architect for Dyaxis II, which uses 9 Motorola 56001's in each chassis to play back and record audio on hard disks and removable (magneto-optic) media. Specify, design, develop, implement, and test DSP algorithms for real-time, high-quality audio production systems. Ported Dolby Labs' AC-2 audio compression algorithm to a 4-processor (40 MHz 56002's) parallel implementation.