Ryan Herbst Email & Phone Number

Redwood City, Ca, Us

Menlo Park, California, Us

Leading a division of engineer and technicians organized into four departments covering silicon sensor design, ASIC design, readout electronics and technician services. Responsible for the development and deployment of photon cameras, high bandwidth RF electronics and high speed data processing electronics using FPGAs.In addition to managing the division I am directly responsible for developments in the following areas: - Edge ML deployment of AI inference engines in FPGAs and ASICs - DAQ and control software development for quantum sensor readout systems for CMBS4 - General purpose hardware control & readout software platform development in Python & C++: github.com/slaclab/rogue

Menlo Park, California, Us

Department head for the Advanced Instrumentation For Research Division, Electronics Systems Department. I manage a team of 30, including firmware, hardware and software engineers, layout technicians and assembly technicians. In addition to management the depart I directly contribute to a number of ongoing projects, including direct contributions in firmware and software development.

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Researched and architected virtualized Cache design. I worked closely with system software engineers in the definition of the design requirements and the command/data flows. Designed, implemented and tested Fibre Channel elastic buffer circuit in a Xilinx FPGA.Designed cost reduced PMC processor card to replace costly off the shelf processor card. This card was eventually integrated into the main system board to further reduce cost.Worked closely with NP software engineers to identify areas of the code that were costing NP CPU cycles due to multiple external memory accesses. I used the findings to architect, document and implement an offload processing FPGA implemented in a Xilinx XCV2000 interfacing to a network processor over a 133Mhz LVCMOS interface. The FPGA consisted of two DDR SRAM interfaces both operating at 133Mhz.Served as the technical lead for the hardware development of Candera’s next generation architecture. This work included a detailed analysis of the traffic flow through the system, identifying the congestion points and detailing solutions for congestion management. My duties also included the scheduling of the hardware implementation from functional specifications through the system implementation and testing. I was responsible for the technical oversight of the overall implementation including schematic design, PCB layout and mechanical design.I personally architected, designed and implemented a SPI4.2 based traffic controller which interfaced our network processor to a SPI4.2 backplane switch. This device also interfaced to a general-purpose processor through a high speed FIFO interface. The main intelligence of this device consisted of a frame lookup engine that would process, modify and route initial Fibre channel command frames as they were received from various hosts.

Technical lead for a team of engineers developing telecom and data processing network equipment.At MAYAN I played a key role in a small team in the design of a 19 card CPCI based chassis product. This included back plane design, support of mechanical engineers and common card interfaces. I also assisted in the early software development of the PCI address mapping and bridge configuration.I designed the central timing card for the Mayan Unifier. This card functions as a system timing source, a CPCI bridge and arbitration card and a platform for attaching an OC3 ring interface daughter card. The timing logic uses a Connor Winfield timing module with a custom state machine implemented in a Xilinx CPLD. This state machine automatically selects between the multiple timing sources available to the system.I designed redundant CPCI arbitration and clock source logic used on the timing and management cards in the Unifier. This circuit contains a custom arbiter implemented in a Xilinx CPLD. This logic allows the redundant PCI system cards to support switching of the arbitration and clocking while traffic is running.I designed T1 interface card for Unifier. This card interfaces 14 electrical T1s to the Unifier SONET back plane.I assisted in the design of system management card. This card contains the same PCI interface logic as the central timing card mentioned above.I designed an HDLC processing card that passes data between 84DS1s on the STS12 back plane and 4 100-FX Ethernet ports. This card contains a DS0 cross connect and an MMC 3400 network processor for layer 3 IP processing.As one of the lead hardware engineers I was involved in system level design discussions while acting as the point contact for system level hardware issues. I was also involved in the architecture design for future projects.

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At Verilink as a junior hardware engineer I supported the design of a 4 port T1/E1 interface card. This card contained a DS0 and signaling cross connect which interfaced data and signaling to the AS2000 back plane. I designed and implemented the signaling cross connect FPGA which sits parallel to the data cross connect device. This FPGA is used to format the signaling data for the AS2000 back plane.I adapted a two port T1 CDSU into a self-contained 1U box.I also supported software engineers in the bringup and coding of various boards, including some low level C coding to configure parts during testing.

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At Verilink I performed card and system level design verification test of T1/E1 CSU and CDSU equipment. I worked closely with design engineers in system verification of new hardware and software. I wrote test plans for verification of new products.I performed testing of new ISDN PRI interface cards. This included setting up and debugging ISDN PRI lines with local telephone company. I wrote 5ESS PRI switch emulation script for HP Idacom test equipment. This test script was used to stress test the ISDN card for multiple call setup and tear down.

Bsee, Electrical Engineering

Electrical Engineering