Experienced Layout (analog, RF and digital) Engineer with over 25 years in industry at locations throughout EMEA, Asia and USA. Project/team management.Full custom analog/mixed signal/RF layout at 28nm, 16nm, 7nm, 5nm, 4nm nodes using DFII, Virtuoso, EXL, VSR. Chip finishing and handover to foundry. Physical verification PVS, Calibre, ICV DRC/LVS/ERC - use, debug, fix. EM and IR drop analysis and fix using Voltus-FI.EDA flow and process improvment and collaboration with other teams to enhance quality and design flow efficiency.Digital layout designs at 65nm and smaller process nodes including customized “Low Power” flows. RTL-to-GDS2 using RTL Compiler, SOC Encounter, QRC extraction.Physical implementation of digital and analog/mixed-signal/RF designs, STA sign-off, formal verification, chip finishing and physical verification. Multiple roles included pre-sales (promoting product features and sales), consulting, implementation, support and training.Managing a team of skilled engineers.Ownership and management of projects through collaboration with sales, marketing, senior managers, finance, legal and operational departments with primary customer contact and responsibility. Project scoping (SOW, sub-contract), planning (budget and time), resourcing (people), execution (implementation), control checklist/ reviews), and project closure (“lessons learned”).Support and mentor (junior) colleagues and customers across different locations remotely and on-site.Specialties: Project management - Prince2™ practitioner qualified.MS Office suite, MS Project, UNIX, Perl, SKILL and Verilog HDL languages