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Amir B. Email & Phone Number
Principal Analog Engineer - AI Silicon Engineering: IP Office
at
Microsoft
1 work email found
@intel.com
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✓ Verified August 2026
4 data sources
Profile completeness 100%
Current company
Role
Principal Analog Engineer - AI Silicon Engineering: IP Office
Location
Sacramento, California, United States
Company size
Who is Amir B.? Overview
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Quick answer
Amir B. is listed as Principal Analog Engineer - AI Silicon Engineering: IP Office at Microsoft, a with 231118 employees, based in Sacramento, California, United States. AeroLeads shows a work email signal at intel.com and a matched LinkedIn profile for Amir B..
Amir B. previously worked as Chief Engineer - Data Center SSD System Integration at Solidigm and Chief Engineer – Data Center SSD System Integration - NVM Solutions Group at Intel Corporation. Amir B. holds Ms, Electrical Engineering from Purdue University.
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*@intel.com
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Profile bio
About Amir B.
Technical leader with breadth of experience and successful track record of leading and delivering on many innovative Intel products/platforms.Technical Expertise:• Design and debug of high performance mixed signal IPs in several generations of silicon process technology (from 180nm to <10nm)• Architecture and design of semiconductor ASIC/SOC products & platforms for PC, mobile and data center market segments• Architecture and design of Industry standard I/O interfaces (HBM2e, DDRx/LPDDRx, PCIe, 112G/56G PAM4 SerDes, Die-2-Die, MIPI, Display-Port etc)• Low power design techniques, tools and flow for mobile SOCs and IPs• Awarded 5 US patents, technical papers published and presented at IEEE and Intel conferences• Opportunity to contribute in several Intel industry innovative products and initiatives like, Multi-Level Cell (MLC) Flash memory, Synchronous Flash memory, Intel’s first integrated graphics chipset (810), Path finding activities towards CMOS BioChipManagement & Operations Expertise:• Build and coached performing teams from grounds up by recruiting key talent and providing opportunities towards professional growth• Developed and maintained schedules for concurrent projects for matrix and globally distributed teams• Experienced in interfacing directly with customers, design service vendors, foundry and Tier-1 IP vendors• Make versus buy analysis for IPs, 3rd Party IP Eco-system enablement (RFI, RFQ, SOWs etc)• Yearly budgets for human resources and silicon debug/validation lab• Experienced in new business incubator/startup environment, collaborating with industry partners on joint projects, leading and working through cross-functional teams
Listed skills include Soc, Semiconductors, Asic, Vlsi, and 27 others.
Current workplace
Amir B.'s current company
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Microsoft
10 roles
Amir B. work experience
A career timeline built from the work history available for this profile.
Chief Engineer - Data Center Ssd System Integration
Current
Dec 2021 - Present
Chief Engineer – Data Center Ssd System Integration - Nvm Solutions Group
Overall technical leader for a Data Center SSD product line with multiple SKUs. Owns driving the Product Requirement Document (PRD) process in collaboration with cross functional team (SSD controller architecture, media, firmware, hardware, system integration and marketing) to deliver comprehensive specification for products that meets customer and market requirements.Responsible for driving product power, performance, latency and QoS modeling and specification across various workloads.
Apr 2020 - Dec 2021
Principal Engineer - Hpc, Ai & Custom Cpu Product Development - Silicon Engineering Group
Responsible for Analog Mixed Signal IPs (specification, sourcing, ASIC integration) for Intel Nervana AI Training ASIC. IPs include: HBM2e 3.2G, PCIe Gen5, PAM4 SerDes, PLLs, Process monitors, Silicon process porting project execution of Intel die-2-die PHY interface over EMIB.
Oct 2018 - Mar 2020
Intel Custom Foundry - Application Engineering /Product Line Management
• Product Line Management for high performance interface IPs• Help build the Analog-IP Application & Solutions Engineering (ASE) team from grounds-up by recruiting key talent. Team provided technical support for foundry customers and external eco-system IP partners• Key contributor in definition of competitive 22nm/14nm/10nm Analog and interface IP portfolio spanning from mobile to enterprise market segments, completed make versus buy analysis for IPs, provided technical and operational support towards IP SOWs award and execution• Lead Analog-IP ASE team in successfully ramp multiple new customers and provided support to existing customers through complete product design cycle (initial product specification/definition to product silicon ramp)
May 2013 - Sep 2018
Atom Soc Group - Hard Ip: Principal Io Power Architect
• Lead definition and deployment of low power design methodologies and tools across various vertical I/O IP teams to meet competitive platform battery life requirements in stand-by and Always-On-Always Connected (AOAC) modes. The IPs were developed on Intel 32nm/22nm/14nm process nodes for SOCs in the Smartphones, Tablets, netbooks, micro-servers, embedded infotainment and digital home markets. • Lead workgroups on power and area scaling of Hard-IP IO and special circuits. Drove path finding activities towards low power circuit architecture and power management features, both in analog and digital domain.
May 2009 - May 2013
New Business Initiatives Group
• Lead path finding efforts for research and development of CMOS BioChip for DNA synthesis and detection market in Intel’s New Business Initiative (NBI) group. • Participated and presented in executive level meetings with external companies for collaboration/SOW on technical information exchange and product development • Lead planning, research and development activities for path-finding and proof-of-concept experiments. Supervised test-chip tape-outs.
Jul 2007 - May 2009
Intel Client & Mobile Chipset Group
Lead the PLL circuits IP and clocking architecture development efforts for Intel’s mobile and desktop chipsets on 180nm to 45nm CMOS processes. These PLLs, associated dividers and clocking circuits were designed to operate at 1-6GHz. Multiple PLL analog cores (Self-Biased CMOS Differential VCO and also LC-tank based) and clocking architectures circuits were developed to meet the clocking (frequency, jitter, power and area) requirements for various I/O and PHY interfaces in Intel desktop and mobile chipsets. For example: Intel Pentium4-Front Side Bus, Intel QuickPath, DDR memory, Serial-ATA1-3, USB2/3, LVDS, HDMI, Display-Port and PCI-Express (Gen1/Gen2).
Jul 1997 - Jul 2007
Intel Memory Component Division
• Participated in the definition and design effort for several Intel Flash products, including the Intel’s first 64-Mbit Multi-Level Cell (MLC) Flash memory and first 16-Mbit Synchronous/Asynchronous Flash memory.• Designed and debugged Address Transition Detection (ATD) based read-path sensing circuits, linear regulators and high-voltage DAC circuits. • Accumulated detailed understanding of Flash cell physics.
Jul 1992 - Jul 1997
Graduate Rotation Engineer
Jun 1991 - Jun 1992
Team & coworkers
Colleagues at Microsoft
Other employees you can reach at microsoft.com. View company contacts for 231118 employees →
MG
Mahan Ghavighalb Kolviri
Colleague at MicrosoftIran, Islamic Republic Of
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NA
Nouman Ali
Colleague at MicrosoftFaisalabad District, Punjab, Pakistan
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NH
Najmul Hasan
Colleague at MicrosoftDhaka, Bangladesh
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SU
Sarah U.
Colleague at MicrosoftRiyadh, Saudi Arabia
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RF
Rob Franco
Colleague at MicrosoftSeattle, Washington, United States
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ND
Noha Daoud
Colleague at MicrosoftEl Zaqaziq, Sharkia, Egypt
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HA
Hamza Ahmed
Colleague at MicrosoftKansas City, Missouri, United States
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JS
Jessica Sierra
Colleague at MicrosoftSeattle, Washington, United States
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RM
Ryan Meehan
Colleague at MicrosoftRochester, Michigan, United States
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TS
Timarra Smith
Colleague at MicrosoftDetroit, Michigan, United States
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Mahan Ghavighalb Kolviri
Colleague at MicrosoftIran, Islamic Republic Of
View →
NA
Nouman Ali
Colleague at MicrosoftFaisalabad District, Punjab, Pakistan
View →
NH
Najmul Hasan
Colleague at MicrosoftDhaka, Bangladesh
View →
SU
Sarah U.
Colleague at MicrosoftRiyadh, Saudi Arabia
View →
RF
Rob Franco
Colleague at MicrosoftSeattle, Washington, United States
View →
ND
Noha Daoud
Colleague at MicrosoftEl Zaqaziq, Sharkia, Egypt
View →
HA
Hamza Ahmed
Colleague at MicrosoftKansas City, Missouri, United States
View →
JS
Jessica Sierra
Colleague at MicrosoftSeattle, Washington, United States
View →
RM
Ryan Meehan
Colleague at MicrosoftRochester, Michigan, United States
View →
TS
Timarra Smith
Colleague at MicrosoftDetroit, Michigan, United States
View →
3 education records
Amir B. education
Ms, Electrical Engineering
Purdue University
Bs With Distinction, Electrical Engineering
Iowa State University
Electrical And Electronics Engineering
Ned University Of Engineering And Technology
FAQ
Frequently asked questions about Amir B.
Quick answers generated from the profile data available on this page.
What company does Amir B. work for?
Amir B. works for Microsoft.
What is Amir B.'s role at Microsoft?
Amir B. is listed as Principal Analog Engineer - AI Silicon Engineering: IP Office at Microsoft.
What is Amir B.'s email address?
AeroLeads has found 1 work email signal at @intel.com for Amir B. at Microsoft.
Where is Amir B. based?
Amir B. is based in Sacramento, California, United States while working with Microsoft.
What companies has Amir B. worked for?
Amir B. has worked for Microsoft, Solidigm, and Intel Corporation.
Who are Amir B.'s colleagues at Microsoft?
Amir B.'s colleagues at Microsoft include Mahan Ghavighalb Kolviri, Nouman Ali, Najmul Hasan, Sarah U., and Rob Franco.
How can I contact Amir B.?
You can use AeroLeads to view verified contact signals for Amir B. at Microsoft, including work email, phone, and LinkedIn data when available.
What schools did Amir B. attend?
Amir B. holds Ms, Electrical Engineering from Purdue University.
What skills is Amir B. known for?
Amir B. is listed with skills including Soc, Semiconductors, Asic, Vlsi, Rtl Design, Low Power Design, Mixed Signal, and Verilog.
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