Amir B. Email and Phone Number
Amir B. work email
- Valid
Amir B. personal email
- Valid
Technical leader with breadth of experience and successful track record of leading and delivering on many innovative Intel products/platforms.Technical Expertise:• Design and debug of high performance mixed signal IPs in several generations of silicon process technology (from 180nm to <10nm)• Architecture and design of semiconductor ASIC/SOC products & platforms for PC, mobile and data center market segments• Architecture and design of Industry standard I/O interfaces (HBM2e, DDRx/LPDDRx, PCIe, 112G/56G PAM4 SerDes, Die-2-Die, MIPI, Display-Port etc)• Low power design techniques, tools and flow for mobile SOCs and IPs• Awarded 5 US patents, technical papers published and presented at IEEE and Intel conferences• Opportunity to contribute in several Intel industry innovative products and initiatives like, Multi-Level Cell (MLC) Flash memory, Synchronous Flash memory, Intel’s first integrated graphics chipset (810), Path finding activities towards CMOS BioChipManagement & Operations Expertise:• Build and coached performing teams from grounds up by recruiting key talent and providing opportunities towards professional growth• Developed and maintained schedules for concurrent projects for matrix and globally distributed teams• Experienced in interfacing directly with customers, design service vendors, foundry and Tier-1 IP vendors• Make versus buy analysis for IPs, 3rd Party IP Eco-system enablement (RFI, RFQ, SOWs etc)• Yearly budgets for human resources and silicon debug/validation lab• Experienced in new business incubator/startup environment, collaborating with industry partners on joint projects, leading and working through cross-functional teams
Microsoft
View- Website:
- microsoft.com
- Employees:
- 231118
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Principal Analog Engineer - Ai Silicon Engineering: Ip OfficeMicrosoftSacramento, Ca, Us
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Chief Engineer - Data Center Ssd System IntegrationSolidigm Dec 2021 - PresentRancho Cordova, California, Us -
Chief Engineer – Data Center Ssd System Integration - Nvm Solutions GroupIntel Corporation Apr 2020 - Dec 2021Santa Clara, California, UsOverall technical leader for a Data Center SSD product line with multiple SKUs. Owns driving the Product Requirement Document (PRD) process in collaboration with cross functional team (SSD controller architecture, media, firmware, hardware, system integration and marketing) to deliver comprehensive specification for products that meets customer and market requirements.Responsible for driving product power, performance, latency and QoS modeling and specification across various workloads. -
Principal Engineer - Hpc, Ai & Custom Cpu Product Development - Silicon Engineering GroupIntel Corporation Oct 2018 - Mar 2020Santa Clara, California, UsResponsible for Analog Mixed Signal IPs (specification, sourcing, ASIC integration) for Intel Nervana AI Training ASIC. IPs include: HBM2e 3.2G, PCIe Gen5, PAM4 SerDes, PLLs, Process monitors, Silicon process porting project execution of Intel die-2-die PHY interface over EMIB.
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Intel Custom Foundry - Application Engineering /Product Line ManagementIntel Corporation May 2013 - Sep 2018Santa Clara, California, Us• Product Line Management for high performance interface IPs• Help build the Analog-IP Application & Solutions Engineering (ASE) team from grounds-up by recruiting key talent. Team provided technical support for foundry customers and external eco-system IP partners• Key contributor in definition of competitive 22nm/14nm/10nm Analog and interface IP portfolio spanning from mobile to enterprise market segments, completed make versus buy analysis for IPs, provided technical and operational support towards IP SOWs award and execution• Lead Analog-IP ASE team in successfully ramp multiple new customers and provided support to existing customers through complete product design cycle (initial product specification/definition to product silicon ramp)
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Atom Soc Group - Hard Ip: Principal Io Power ArchitectIntel Corporation May 2009 - May 2013Santa Clara, California, Us• Lead definition and deployment of low power design methodologies and tools across various vertical I/O IP teams to meet competitive platform battery life requirements in stand-by and Always-On-Always Connected (AOAC) modes. The IPs were developed on Intel 32nm/22nm/14nm process nodes for SOCs in the Smartphones, Tablets, netbooks, micro-servers, embedded infotainment and digital home markets. • Lead workgroups on power and area scaling of Hard-IP IO and special circuits. Drove path finding activities towards low power circuit architecture and power management features, both in analog and digital domain.
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New Business Initiatives GroupIntel Corporation Jul 2007 - May 2009Santa Clara, California, Us• Lead path finding efforts for research and development of CMOS BioChip for DNA synthesis and detection market in Intel’s New Business Initiative (NBI) group. • Participated and presented in executive level meetings with external companies for collaboration/SOW on technical information exchange and product development • Lead planning, research and development activities for path-finding and proof-of-concept experiments. Supervised test-chip tape-outs.
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Intel Client & Mobile Chipset GroupIntel Corporation Jul 1997 - Jul 2007Santa Clara, California, UsLead the PLL circuits IP and clocking architecture development efforts for Intel’s mobile and desktop chipsets on 180nm to 45nm CMOS processes. These PLLs, associated dividers and clocking circuits were designed to operate at 1-6GHz. Multiple PLL analog cores (Self-Biased CMOS Differential VCO and also LC-tank based) and clocking architectures circuits were developed to meet the clocking (frequency, jitter, power and area) requirements for various I/O and PHY interfaces in Intel desktop and mobile chipsets. For example: Intel Pentium4-Front Side Bus, Intel QuickPath, DDR memory, Serial-ATA1-3, USB2/3, LVDS, HDMI, Display-Port and PCI-Express (Gen1/Gen2).
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Intel Memory Component DivisionIntel Corporation Jul 1992 - Jul 1997Santa Clara, California, Us• Participated in the definition and design effort for several Intel Flash products, including the Intel’s first 64-Mbit Multi-Level Cell (MLC) Flash memory and first 16-Mbit Synchronous/Asynchronous Flash memory.• Designed and debugged Address Transition Detection (ATD) based read-path sensing circuits, linear regulators and high-voltage DAC circuits. • Accumulated detailed understanding of Flash cell physics.
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Graduate Rotation EngineerIntel Corporation Jun 1991 - Jun 1992Santa Clara, California, Us
Amir B. Skills
Amir B. Education Details
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Purdue UniversityElectrical Engineering -
Iowa State UniversityElectrical Engineering
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Ned University Of Engineering And TechnologyElectrical And Electronics Engineering
Frequently Asked Questions about Amir B.
What company does Amir B. work for?
Amir B. works for Microsoft
What is Amir B.'s role at the current company?
Amir B.'s current role is Principal Analog Engineer - AI Silicon Engineering: IP Office.
What is Amir B.'s email address?
Amir B.'s email address is am****@****tel.com
What schools did Amir B. attend?
Amir B. attended Purdue University, Iowa State University, Ned University Of Engineering And Technology.
What skills is Amir B. known for?
Amir B. has skills like Soc, Semiconductors, Asic, Vlsi, Rtl Design, Low Power Design, Mixed Signal, Verilog, Pcie, Cmos, Ic, Physical Design.
Who are Amir B.'s colleagues?
Amir B.'s colleagues are Gurkirat Bhangu, Daniel Yehdego, Phd, Michelle Belgau, Shamheed A, Qin Nina, Mike Branat, Qian Zhuge.
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