Amit Srivastava Email & Phone Number

I lead the development of next generation low power architecture. I have a solid background in software development with more than 15 years of experience in architecting and delivering large and complex projects in C/C++. I have been a Project lead in Mentor Graphics in the past, leading the Questa PASim team. I also participates in IEEE 1801 UPF, actively contributing the next revision of the IEEE standard. I have two granted US patents, one in software algorithm as a sole inventor and another in user methodology as co-inventor. I have authored several papers in low power area, including the best paper at DVCon 2009. I was part of Technical Program Committee of DVCon-India 2014 and also the session chair of low power track at DVCon-India 2014. Specialities: C/C++, Algorithms, Datastructures, Design Patterns, UPF, Power Aware Verification, Low Power Verification Methodologies, UML, VHDL, Verilog

Listed skills include Eda, C, Algorithms, Data Structures, and 12 others.

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  Indian Institute Of Technology (Banaras Hindu University), Varanasi

  Electronics