Amol Agarwal Email & Phone Number

More than 17 years of experience in ASIC chip design with strong understanding of overall chip design flow,concepts and challenges. Specialty in Physical design with hands-on experience in physical design aware architecture definition, clocking architecture, interconnects, high speed IO interfaces, STA & timing closure, logical and physical synthesis, DFT , silicon debug.Lead successfully multiple complex projects for automotive applications from RTL to GDS on 55nm, 40nm, 16ffc and 5nm tech nodes7 US patents issued so far and 20+ articles and publications in leading VLSI conferences and publication platforms

Listed skills include Design, Physical Design, Physical Synthesis, Static Timing Analysis, and 7 others.

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  Indian Institute Of Technology (Banaras Hindu University), Varanasi

  Electronics And Communications