I focus on standard cell benchmarking and PPA optimization for groundbreaking technologies like Intel 18A GAA RibbonFET and Intel3. With a tool we developed, we're pushing the boundaries of technology maturity and exploring DTCO pathways to meet diverse product specifications.The collaboration with the technology development team is instrumental in evaluating and optimizing PPA to align with product needs. My expertise in SPICE and Monte Carlo analysis and a solid background in NVM device integration and yield engineering ensures that we continually advance Intel's competitive edge in the semiconductor industry.Skills:Programming & Scripting: C++(MPI, OpenMP), Python, JMP Script, MATLAB, Perl, Tcl, BashHDL: System Verilog, VerilogLab Experience: Electrical characterization (materials), CV/IV (transistors), Memory ATE (magnum V tester & computer-based bench testing), Thermal imagingCircuit Simulation & Layout Design: hSpice , VirtuosoRTL2GDS flow (via cadence-certificate): basic knowledge of xcelium, Genus, Innovus ,TempusBasic Static Timing Analysis (via cadence certificate)