I focus on standard cell benchmarking and PPA optimization for groundbreaking technologies like Intel 18A GAA RibbonFET and Intel3. With a tool we developed, we're pushing the boundaries of technology maturity and exploring DTCO pathways to meet diverse product specifications.The collaboration with the technology development team is instrumental in evaluating and optimizing PPA to align with product needs. My expertise in SPICE and Monte Carlo analysis and a solid background in NVM device integration and yield engineering ensures that we continually advance Intel's competitive edge in the semiconductor industry.Skills:Programming & Scripting: C++(MPI, OpenMP), Python, JMP Script, MATLAB, Perl, Tcl, BashHDL: System Verilog, VerilogLab Experience: Electrical characterization (materials), CV/IV (transistors), Memory ATE (magnum V tester & computer-based bench testing), Thermal imagingCircuit Simulation & Layout Design: hSpice , VirtuosoRTL2GDS flow (via cadence-certificate): basic knowledge of xcelium, Genus, Innovus ,TempusBasic Static Timing Analysis (via cadence certificate)
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Staff Design Enablement Engineer (Standard Cells Benchmarking And Ppa Optimization)Intel Corporation Jan 2024 - Nov 2024I am working on standard cell benchmarking for different intel technologies (Intel 18A GAA RibbonFET), Intel3 ..etc. We developed a python-based tool to generate hspice flows to evaluate std cell PPA (leakage power, Dynamic Power & Delay) for both combinational &sequential cells. it includes the capability to explore the impact of random variation via Monte Carlo as well as Vt targetting. using this tool, we evaluate technology maturity across PDKs and we also explore pathways (DTCO) for PPA optimization to fit diverse products specs in collaboration with the technology development team. -
Nvm Device Integration & Yield EngineerIntel Corporation Jan 2021 - Dec 2023Device Engineer at Intel Corporation leading research and development in order to develop industry-leading NAND Flash memory technology. The scope includes hands-on characterization, modeling of the observed NAND memory device/array characteristics, and engineering solutions to achieve the highest level of NAND memory component performance, quality, and reliability. Key achievements: (1) I have developed high-endurance SLC as a cache for first 5bit/cell NAND. product has been qualified. we published the work in ISSCC'23/IEEE SSC-Letters (2)I have co-authored one conference paper (Intel conference for Advanced Analytics) on the use of machine learning for corner-case reliability testingCareer development skills: I attended the Talent Keepers leadership program (four month offered by Intel) to leverage leadership skills.
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Module Yield And Integration EngineerIntel Corporation Oct 2017 - Dec 2020Performing a variety of technical duties required for process development, detecting and resolving non-routine equipment or process errors, and ensuring product quality. Proficiency using SPC, PCSA, DOE, and JMP. Qualify new platforms needed for ramping factory capacity and technology-driven process change with the goal of product yield improvement and cost reduction. Led task force meetings with vendors for defect reduction on newly-qualified platforms.
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Research AssistantPurdue University Jun 2012 - Aug 2017Lafayette, Indiana AreaMy doctoral dissertation is about developing a new model to study the non-diffusive thermal transport. We developed truncated Lévy model to interpret the quasi-ballistic thermal response experimentally observed by time domain thermoreflectance method (TDTR).The model leads to improved thermal characterization of nanoscale devices and material interfaces.By analogy to engineering superdiffusion in light (Lévy glass), we have used the nanoparticles embedded semiconductors with varying concentration to study the impact of nanoparticles on the superdiffusive thermal transport. In addition, I have worked on a project to study the self-heating of hybrid graphene -silver nanowires network (used as transparent conducting electrodes) using thermoreflectance imaging. In this project, I developed a statistical analysis framework to analyze the temperature distribution of nanoscale networks with interesting insights on the non-linear percolation theory and reliability physics of nanoscale networks. -
Research AssistantBirck Nanotechnology Center 2012 - 2016 -
Summer Research InternOak Ridge National Laboratory May 2015 - Aug 2015Oak Ridge, TnCharacterization of the thermoelectric/thermal properties of Tin Selenide (SnSe) for different crystal orientations using ZEM3 system and laser flash method. -
Phd StudentUc Santa Cruz Jan 2012 - Jun 2012 -
Teaching AssistantCairo University Sep 2008 - Dec 2011 -
Teaching AssistantAmerican University In Cairo Sep 2008 - May 2010Cairo Governorate, Egypt
Amr Mohammed Education Details
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4.0/4.0
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3.90/4.0
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90.75/100
Frequently Asked Questions about Amr Mohammed
What is Amr Mohammed's role at the current company?
Amr Mohammed's current role is Design Engineer |Physical Design |PPA| Standard Cells benchmarking| Memory Technologies |Semiconductor Devices| Reliability Physics| Manufacturing.
What schools did Amr Mohammed attend?
Amr Mohammed attended Purdue University, Cairo University, Cairo University.
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