Focusing on designing RISC-V processors with M extension and privileged architecture.Working with DSP team to implement DSP blocks for wireless communication such as FFT, Viterbi decoders, and digital filters.Create Matlab models for wireless communication systems (PSK modulation, channel coding, interleavers, frame sync, etc)Providing expert consultancy for ASIC SoC backend design, ensuring efficient and high-performance designs.Building new CAD flow for digital team.

Handle PnR CADR&D for new topics/tools/flowSupporting critical challenges in running projects

Work as a contractor for Synopsys on multiple IPs: DDR PHY IP, DDR CTRL IP, DDR Subsystem Integration, HBM IP, and Bluetooth Low Energy IP, on multiple tech nodes from 40nm down to 5nm.

Building an SoC on Altera FPGA using an embedded processor, DMA, and SATA IPs

Design of high-speed accelerator of Squeeze-Net convolutional neural network architecture on Xilinx Virtex-7 FPGA. Sponsered by Mentor Graphics, One Lab, and ASRT.

Testing of CDC and Lint tools @ Questa Formal team (QFT)