Visionary Technology R&D Executive with over 28 years of technical and leadership experience in advancing Moore's law of transistor scaling. Varied roles across semiconductor process technology development including novel epitaxial deposition and metallization for Si, SiGe channel and Gate All Around (GAA) RibbonFET transistors. Applied deep expertise in semiconductor fabrication process technologies across 10 nodes, positively influencing product design and high-volume manufacturing in semiconductor fabs. Fostered strong integration and collaboration with suppliers and research consortia, contributing significantly to process technology leadership, product advancements and profitability.Co-authored in more than 50 technical publications and holds 313 U.S. patents granted for pioneering work in the fabrication of CMOS and HBT transistors based on Si, SiGe, Ge and III-V compound semiconductor materials.