Antonio Chaides Email & Phone Number

Santa Clara, California, Us

Santa Clara, California, Us

· Developed post-silicon validation test content for a next generation AI processor, focusing on network performance and functionality. Using a C++ based software library to interface with the AI accelerators to conduct tests within commercial operating systems, ensuring the reliability and efficiency of AI hardware in real-world environments.· Provided test content for post-silicon at scale validation for multiple IPs, including but not limited to: CXL, interrupt controller, virtualization, and monitoring features. Collaborated on failure debug identifying part defects, software issues, or silicon bugs.· Collaborated with cross-functional teams outside of my main SoC Functional Validation Engineer responsibilities to support the pre-silicon test plan verification effort for a CXL.Cache and CXL.MEM IP in a next-generation server program. Enabled UVM testbench environments and wrote UVM sequences for directed test case verification.

Santa Clara, Ca, Us

· Created full SoC emulation models and supported pre-silicon validation for the Ampere Altra Armv8.2-Aproduct family for the datacenter using Cadence’s Palladium Z1.· Integrated emulation collaterals and path-cleared reset and IP bring-up from early boot stages until Linuxboot, delivering sanitized emulation platforms for validation stakeholders.· Collaborated in bug resolution, providing feedback to hardware/software developers and Cadence applicationengineers by means of, but not limited to: collecting waveforms and AMBA bus monitor logs.· Supported early development firmware readiness enabling for a proprietary system interconnect as well astools for memory preloading and/or filelist manipulation for emulation build automation.

Santa Clara, California, Us

· Led a team responsible for developing full-system SoC emulation models, supporting pre-silicon validation foran Xeon-D microserver using Synopsys’s ZeBu Server 3.· Drove key milestones in reset and early boot stages for an Intel's Xeon-D microserver, enabling core firstfetch and early BIOS boot. Collaborated across multiple 10nm Intel server product lines, ensuring deliveryof optimized emulation platforms for validation teams, providing critical feedback to logic designers.· Supervised the integration of emulation models tailored to specific validation requirements, covering key areassuch as DDR, PCIe, power management (PM), BIOS, soft/warm reset, coherency, and reliability, availability,and serviceability (RAS).· Received a Division Recognition Award in February 2018 for excellent cross site collaboration in enabling firmware to complete boot flow for the first time for a next.generation micro server program.· Received a Division Recognition Award in February 2017 for a valuable contribution in enabling boot flows for a network controller IP for the first time in simulationand emulation.