Anders Berglund Email & Phone Number

Santa Clara, California, Us

Sr. Manager Front-End SoC Design responsible for RTL Design, IP Integration and Quality Checks delivering Design Database to partner Teams in a timely manner with high quality.The Team worked on Designs including Neural Network Processor Chip for Machine Learning and next generation P-Cores and E-Core for Data Center for High Performance Compute and Efficient Compute respectively, with the focus on DDR5 and Inter-Die High speed communication Tiles. The RTL Design database resulted in high quality Silicon with record short Power-On bring up and booted several OS in record short time with excellent Silicon health.

Altera/Intel PSG 2013 -2018 (Altera acquired by Intel):Sr. Manager Factory Application Engineering responsible for Worldwide support for Quartus II, OpenCL, High Level Synthesis as well as support for Tier 1 customers.Grew the Team significantly as more support was needed for expanded early adopter programs. The Team Successfully supported the roll out of Arria 10 and Stratix 10 devices. The team developed a customized workshop for RTL optimization geared towards Stratix 10 and trained 150+ FAE’s worldwide receiving a 95% satisfaction score.

Sunnyvale, California, Us

Managed local teams of about 10 engineers in different disciplines such as Analog Mixed Signal, Functional Verification, Static Timing Analysis, Test (DFT, ATPG) and FPGA-SynthesisManager responsibilities includes organizing efficient pre- and post sales support for Silicon Valley region including hiring and retaining top talents; experience managing teams under times of transitions such as acquisitions, new product roll out and change of directions;Extensive experience working with customers to understand requirements, define enhancement to meet new demands such as Circuit Simulation for 3DIC, developing efficient DFT/ATPG flow for custom digital logic etc.Additional program manager responsibilities, organized:- Silicon Valley SNUG (user conference)/AMS track: 2-3 day programs of user papers and tutorials covering co-simulation, SI analysis, circuit checks, characterization, post layout simulation challenges, reliability analysis such as IR drop, Electro Migration, silicon aging and more; program attendance grown year over year to several 100 engineers;-Training for application engineers at worldwide events such as Synopsys field conferences and annual training sessions; worked with Business Units and field organization to ensure training needs were met

First FAE responsible for pre-sales support of Solidify (static functional Verification); successfully conducted several evaluation resulting in new logos; created and delivered training material; built up a FAE team and trained European sales distributors; defined support model, purchased CRM software and customized it to meet the organization’s need

Waltham, Ma, Us

Responsible for pre-sales support of Lexra's IP LXR-4080, synthesizable MIPS core; successfully concluded an evaluation resulting in the company's largest order of $1.5MIdentified critical Synthesis/Testability enhancement required for broader adoption resulting in support for Memory BIST and better Synthesis/DFT flow; used Altera’s MAX PLUS II to implement a FPGA prototype flow with fixed pin out specification which enabled the customer to design the PCB ahead of the IP delivery schedule minimizing end product lead time.

Sunnyvale, California, Us

Silicon Valley: Regional Synthesis, Test (DFT, ATPG) and Arkos expert (emulation) Stockholm office:Wide area of responsibilities such as pre-sales support, support center function; delivering multi day Synthesis and Test training internationally; internal IT support and license managementSupported many tools such as Design Compiler, PowerCompiler, TestCompiler; TetraMax, VSS (VHDL simulator); ModelSource (hardware modeler with I/F to simulators, Arkos (emulator), Behavioral Compiler (behavioral synthesis), HDL Advisor, SmartModels, Cyclone (VHDL cycle base simulator) and more.

Kista, Stockholm, Se

CAD responsibilities:EDA tool installation and environment to access tools and libraries; license management and monitoring, synthesis libraries modifications; organized trainings; performed evaluationsDeveloped design flow including Verilog RTL coding methodology and advanced synthesis/DFT scriptingASIC design:block design formatting proprietary telecom protocol to standard protocol from specification to gates including functional verification, synthesis, DFT insertion, code documentation and code peer reviews.

Designed 20GHz bandpass filter using coplanar wave guidelines and EEsof simulator, created report of design characteristic, design challenges and issues with manufacturing variability effecting mainly inductors