Lead architect for driving architecture definition, digital IP development, implementation and verification of state-of-the-art O-RAN compatible LowPHY processing engine for use in a complete and first-to-market O-RAN compliant O-RU SoC silicon solution with integrated RF transceivers.Worked as one of the architect leads in a large (+300 people) cross-discipline team consistingof members from marketing, digital and analog design, physical/layout design, verification, software,product evaluation and applications teams to reach tape-out of an industry-first 4T4R O-RAN compliant ASIC.Areas of responsibility :+ Architecture and product requirement definition:- Driving the architecture definition and specification documentation- Defined silicon-agnostic and modular LowPhy engine architecture targeting various FPGA prototypeplatforms and silicon tapeouts+ Digital IP development and implementation:- Designed a fully O-RAN compatible 5G LowPhy processing engine incl OFDM modulators, PRACHprocessing and various DSP functions- Designed commercial- and ASIC-grade IPs and digital modules- Assisted physical design teams in adopting the silicon-agnostic LowPhy IP to a 16nm ASIC process nodeincluding memory, scan, mbist insertion, etc.- Assisted digital verification team in closing verification of the LowPhy IP to an ASIC grade with fullcode and functional coverage+ Leading effort in:- Educating marketing, application and product evaluation teams in the field of O-RAN, 4G/5G andwireless- Acting as supervisor for several master thesis at DTU within the area of DSP and wireless communications- Driving initiatives for improving internal development work flows and processes such as documentationand quality standards for digital development- Establishing standards on how to structure IP user guide and documentation for interfacing with SWteams- Ensure important milestones and targets were met for reaching critical ASIC tape-out dates

Development of designs, planning, implementation, verification and documentation of IP-cores and systems within communication with a special focus on digital signal processing and 4G/5G wireless products.Areas of responsibility :+ IP development:- LowPhy for Radio Protocol (LTE + New Radio) PHY processing- OFDM modulator/demodulators incl. FFT/iFFT- RS-FEC for CPRI and Ethernet- IQ Compression- Digital Up/Down Conversion- Digital verification through functional simulations+ Hardware platform development:- Worked with state-of-the-art AMD/Xilinx and Intel/Altera FPGA development boards- System development in Vivado and Quartus with integration of in-house IPs- Custom O-RAN O-RU prototype platform development- Transceiver setups- Hardware verification and testing in lab+ Sysem-on-Chip development- Design and development of components for a full SoC project in a larger team- Produced design specifications and user manuals- Set up of simulation based test environments- Offered remote and on-site support for costumers+ Leading effort in:- Defining internal guidelines for efficient and structured work flow for digital development- Developing internal digital libraries- Establishing a Continuous Integration flow for QA