Andrea Bartolini Email & Phone Number

Bologna, It

Bologna, Emilia Romagna, Italia

Andrea Bartolini leads the activities of a small group of young researchers and graduate students, with focus on resource management for multi- and many-processor systems on a chip. This includes Power/Energy, Thermal and Reliability management: exploring both advanced model predictive DVFS, workload allocation policies, self-tuning model extraction and their efficient implementation in the standard software stack. Andrea Bartolini is the main technical contact for the 7th Framework Program project PHIDIAS, funded by the EU, which aims to explore and develop new ultra-low-power architecture, design and run-time strategies for Smart Bio-signals Computing Platforms based on Compress Sensing. He the main technical contact for the ERC Advance project MULTITHERMAN, funded by the EU, which aims to explore and develop solutions for the upcoming Thermal Crisis of the Digital Electronic Devices. He was sub-contractor for the 7th Framework Program project THERMINATOR, funded by the EU, aimed to develop new design and run-time technologies to mitigate thermal issues in future electronic devices.

Within a collaboration framework on developing energy efficient runt-time policies for the Intel Single-Chip Cloud Computer (SCC) device, research activities focused on investigating the software stack to monitor the energy consumption of SCC and the workload MPI-communication pattern. In addition I have developed a set of models based on Neural Networks and System Identification algorithms to predict the energy consumption of a given MPI parallel benchmark based on its runt-time characteristics. In addition I have developed a set of new energy savings DVFS run-time policies.

Within a project to design advance control strategies for dynamic resource management in multi-core platform, research activities focused on investigating program phases in PARSEC benchmarks and design powerful and lightweight Linux O.S. modules for profiling workload changes and characteristics by exploiting the HW performance monitors in an SMP server platform. The results as been used to create an empirical power, thermal model of the characterized platform and a performance model of the examined workload.

Within the XEC project to design energy saving algorithm in the O.S. of mobile/multimedia SoC, research activities focused on prototyping dynamic luminance scaling algorithm to save backlight energy in LCDs display.

Phd, Ingegneria Elettronica

Laurea Specialistica, Ingeneria Elettronica