My Ph.D. research focuses on techniques that aid the process of scheduling and resource management in the presence of heterogeneous hardware, via accurately predicting upcoming runtime events. With a proactive and accurate view of the near future, schedulers can utilize the underlying hardware more efficiently, and fully take advantage of the available benefits.By adapting a majority element heuristic, we significantly improve the accuracy of predicting memory addresses about to be accessed, while reducing prediction-related costs by a factor of ten thousand compared to previously proposed predictive approaches. Coupled with novel microarchitectural modifications, accurate address predictions are shown to improve the performance of heterogeneous memory architectures.Machine learning-based performance predictors are further presented, capable of predicting a program's performance when executed on a given general-purpose core. Trained to model the subtleties of the interaction between hardware and software, these predictors are capable of generating highly accurate predictions even for cores with varied Instruction Set Architectures. Utilizing these performance predictions for job scheduling, is shown to improve overall system performance. Finally, I quantitatively demonstrate that scheduling algorithms cannot guarantee deriving an optimal schedule during realistic execution scenarios due to the underlying hardware heterogeneity, the wide range of runtime requirements of software, as well as prediction error from performance predictors. In response, deep neural networks are trained to select one scheduling approach from a list of options with varied overheads and correctness guarantees. The scheduling approach chosen, is the one which will most likely return the highest-performance schedule with the lowest overhead, given a particular instance of the job-to-core assignment problem.

Performance analysis, focusing on setting expectations on future generations of AI accelerators.

Implementation of a statistical memory simulator.- Implemented a tool capable of extrapolating the behavior of large memories aftersimulating tiny memories.

Research in dynamic memory management in hybrid memory configurations. - Developed dynamic memory management mechanism focusing mainly on scalability to very large memory capacities. - Utilizing a "Majority Element Algorithm" heuristic for extremely efficient activity tracking.This work was accepted for publication at the IEEE International Symposium on High Performance Computer Architecture (HPCA), 2017.

My responsibilities as a researcher included defining an efficient reliability mechanism and implementing it in high-level simulator in order to assess its fault coverage.This research led to a reliability mechanism for Networks-on-Chip. This work was accepted for publication at the International Symposium on Microarchitecture (MICRO 2012).

Implemented a cycle-accurate event-driven Network-on-Chip simulator with a Graphical User Interface, allowing for record-and-play debugging of complex NoC models.

As an undergraduate research intern, I evaluated and compared several Network-on-Chip simulators in an attempt to identify their individual benefits as well as drawbacks.