Investment Platform for startups at any stage with minimum risks & maximum benefits to all parties with improved trading liquidity of stock exchange. The platform, as next generation crowdfunding, resolves the problem of first/lead investor for perspective startups based on innovative financial and trading algorithms. The platform is planned also to provide jont liquidity of fiat stock exchange and cryptocurrency investments in funding new projects.

Syntec develops ASIC synthesis methodology to significantly reduce by factor 2-10x and more of power consumption and heat for high performance and Low-power chips. The solution will not occupy significant chip area with more then 30% of clock speed improvement because of possibility to better optimization. This is currently the most serious issue for semiconductor industry to improve overall calculation performance with limited power consumption, for example, server/ mobile/ AI / IoT processors, VR/AR devices, etc.

Securter Inc is game-changing, technology-driven start-up that develops next generation patent pending payment / authentication platform for card present online payments and banking which proposes significant advantages for all sides of the payment process (Credit Companies / Banks / PSP, Merchants, Consumers) regarding to competing solutions. The proposed platform can be also complementary for different market directions, for example, Digital ID and Authentication (e-Government), IoT, Cloud/Big Data, Blockchain/Bitcoin, Smart Cites, Connected Cars and other technologies that require secure and reliable online user authentication.Highlights:- Best security level at lowest payment processing cost - Strong and versatile business model/vision and multidisciplinary team - Convenient use for online merchants and shoppers - Solves fraud and cart abandonment issues- Solves volatility / legality / security / chargeback / anonymity / cost issues for Blockchain-based platforms

PureSignal develops new generation of radio receivers based on patent-pending Dynamic Radio Filter (DRF) technology to significantly improve signal to noise (SNR) performance of a various analog and digital modulation-based receivers and standards, such as Ultrasound Scaners and Receivers, Medical Telemetry Systems, Wireless, Cellular, FM tuners, Military, Radar/Lidar, GPS receivers and more.The technology is intended to significantly improve noise filtering quality for a variety of applications that are based on Low/Band-Pass Filters (LPF/BPF).The algorithm utilizes a posteriori information that is not utilized in conventional schemes and allows 3...6 dB SNR improvement for exists and new receiver's schemes.The improved SNR is equal to higher data quality and speed, lower transmittion power or more communication distance.The algorithm was successfully simulated in Matlab and mathematically proven by leading expert in the field of radio receivers and signal processing.

SFTD is intended to solve verification and validation problem of processors and SoC both in R&D and fabrication stages. This technology allows fastest, very reliable and low cost mutual self- testing of processor’s chip without any use of additional test circuits on a chip as BIST and DFT, which are occupied up to 15% of total chip area and also decrease total chip performance of about 5%. DFT also causes to up to 15% of wrong rejection of fully serviceable processor’s chips and low yield following to faults which falls to DFT circuit itself. In addition, DFT is decrease yeild of 5-10% by detection of Logic Redundancy faults which haven't any effect to system functionality.

Next generation radar signal processing to improve performance and overcome limitation of conventional high resolution radars.

New generation of highest-efficient AC-DC converters for power supply of modern electronic devices with 95% and more of power efficiency at low cost, small size, high quality and stability of output current/voltage.New electrical scheme is based on proven theoretical basics with applying digital signal processing algorithms. The proposed solution would solve disadvantages of well-known market solution and would be applied for any power ranges.

Semi-automatic, portable and computerized ultrasonic device to controlled clearing of blood vessels from any type of thrombus for emergency medical services. The target device is intended for fast and effective removing different types of thrombus to prevent Acute Total Occlusions such as heart attack, stroke (“brain attack”) and also Chronic Total Occlusions in which blood supply to a part of the heart, the brain or coronary arteries is suddenly or chronically interrupted.

Develop powerful processor FAD (Flexible Arithmetic Datapath) architecture and methodology which combines advantages of programmable MIMD(Multiply Instruction Multiply Data) instructions and on-a-fly FPA (Field Programmable Arrays) hardware reconfiguration within single processing core to reach the best MIPS per Watt performance ratio for next generation data processing core architectures.

Fastnet Communication is an early-development stage start-up company which is engaged in development next generation ultrafast PHY digital data communication interconnects and interfaces for a variety electronic devices requiring ultrafast, low-cost, high-quality, low-latency and low-power consumption digital data interchange that is based on low-complexity ultra high-speed forward error correction (FEC) schemes. The other R&D direction is improvement of SOVA (Soft Output Viterbi Algorithm) to close to MAP algorithm BER performance at hardware complexity of SOVA. The target product is a next generation for USB / SATA / PCIe / InfiniBand / Rambus / HBM memory / HyperTransport-like PHY communication controller (Mixed ASIC IP Core / Chipset) with 30 Gbps and more data throughput per single cooper (or optical / wireless) lane with at least 50 times lower power consumption per transmitted bit because of utilization more robust modulation scheme and new low-complexity powerful FEC algorithms.In contrast, conventional high-speed binary pulse-based transmission links which are based on binary pulses are limited to 5..10 Gbps per twisted pair lane.It is possible also to obtain at least 50 times lower power consumption for current generation of 5..10 Gbps interconnects at significantly lower latency.Markets & Applications for next generation PHY level interconnect solution: Data Servers and Storage System, High-Speed / Low-Power Memory / BUS Controllers for DSP / GP / Graphical / Network Processors, SoC / CoC, Wire / Wireless / Optical Interconnects, Computing Boards / Adapters.