Founder of mbstech YouTube channel, which has a primary focus on electronics education and development

Design of Complex PCB and high speed digital electronics. FPGA's normally used are POLARFIRE , IGLOO2 A3P. Normally flash based FPGA's unsed in harsh SEU environments.Design of Control and Monitoring functions for motor drive control. Typical electronics would normally include high speed MANDEC (Custom control of RGMII interfaces for low latency networking) Fault tolerant design, Isolated and non-isolated functions (ADC, CAN, RTD's Resolver interfaces ETC..)Gate level reviewing, Mentor and guidance support to engineering.

Electronics HW discipline ChiefPromoted to discipline Chief (Electronics) to support the groups Motor control electronics. Role also included that same as previous consultant level job.

Promoted to Consultant, and Goodrich was taken over by UTC. My role continued to design Hirel electronics for a multiple of platforms some mentioned here are 787 EBAC, KC390 Military Transport. My main role was to deign complex control and monitoring functions for Motor drive applications which included, requirements capture in DOORS or Polarion, Teams center. Job requirements also included schematic design and the complex PCB design to implement the function, this also included FW to test the application (VHDL). Other roles and duties due to being a senior engineer was the mentor and guidance to others so product quality and functional performance was kept at a high level. Gate level reviewer and signatory.Many of the systems were design with careful consideration to harsh environments, life cycle management, SEU mitigation / robustness, isolation of functional systems and common mode fault mitigation.

Joined Goodrich's Electromagnetic's Systems Technical Center. Primary role was the design and development of motor control electronics for new motor drive systems and to support current programs.This includes the design of any analogue or digital electronics that performs the control and monitoring functions in a motor drive system.Designs include ESMCU Engine Start Motor Control Unit (Control and Monitor Electronics and PCB) Support for the A350 ETRAC Engine Thrust Reverse Actuation Controller.Systems level architecture design for motor control applications,fault tolerant design and design of high speed digital systems with regards to SEU and harsh enviroments.

Design of continuous and transient based health monitoring systems for aerospace engine control applications. This system used the latest PowerPC and DSP/FPGA technologies and chipsets to present a highly parallel architecture which when implemented gave a very high processing bandwidth. VHDL IP written included DFT, windowing functions, spectral density functions, adaptive tracking filters which locked on to engine harmonics. FPGA to PowerPC using PCI interface + FPGA to DSP links. The design was based on a concurrent cell based architecture with redundancy. The FPGA's used were Actel and Xilinx based.EMS specialist and technical lead engineer for health monitoring systems for the T56 Advanced Hawkeye Engine Monitoring Systems. Concept design of prototype card.Design of complex high speed mixed signal electronics, which included concept, schematic and layout of design using Altium Designer.Design of electronics for harsh environments and system level SEU robustness.

Senior Design Engineer working in the RnD department at Goodrich Engineer Controls. Design of Mixed signal electronics for HiRel aerospace products. Systems include Flight Actuation control's, Design of firmware for technology applications + Complex multi-layer PCB design using Protel / DXP designer (now Altium). My job was mainly developing the complete system which included the firmware and hardware to demonstrate to application. Actuation controls ( FW + ASIC development cards) to support A380 motor controls for Goodrich Electromagnetic's Systems Technical Center.

Design of production level test equipment for 16 and 32 bit X86 and ARM based processors including FPGA design for that architecture. Integration and control of equipment using Labview under the Test-stand architecture and test executive. Integration of mixed processor FPGA products and designing subsystems on current products. Platforms included were lucent ORCA 3T and Phillips Cool Runner series of CPLD's. Subsystems on chip included AC97 Audio Codec's , Touch Screen's 4Mbit Fast IR interfaces, MMC cards etc..

The design and test of IP solutions for the Mentor Graphics Inventra Group. This involved writing VHDL IP and designing a test platform using Mentor Graphics software (Board Station / Design Architect) for IP demonstration. IP designs from 100k to Million gate designs using Flex 10K series FPGA's.