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Andrew Dearborn Email & Phone Number

Principal ASIC Engineer (HPC CAD) at Tokyo Electron US
Location: Austin, Texas Metropolitan Area, United States 9 work roles 3 schools
1 work email found @tel.com 2 phones found area 415 and 888 LinkedIn matched
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Current company
Role
Principal ASIC Engineer (HPC CAD)
Location
Austin, Texas Metropolitan Area, United States

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Andrew Dearborn is listed as Principal ASIC Engineer (HPC CAD) at Tokyo Electron US, based in Austin, Texas Metropolitan Area, United States. AeroLeads shows a work email signal at tel.com, phone signal with area code 415, 888, and a matched LinkedIn profile for Andrew Dearborn.

Andrew Dearborn previously worked as Senior Staff CAD Engineer at Mythic and Senior Staff CAD Engineer at Mythic. Andrew Dearborn holds Ba, History / Business from Ucla.

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{first}.{last}@tel.com
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Profile bio

About Andrew Dearborn

Innovative Full-Stack Programmer with 25 years of experience in the semiconductor industry, covering a broad range of VLSI disciplines. Current expertise in R&D of internal EDA tools targeting various domains, using various programming languages, EDA tool interfaces and Open-source APIs; cross-functional collaboration, design automation, data structures, algorithms, GUI and concurrent flow architecture. Extensive experience managing EDA tools, collaborating with vendors on new features and training Engineers in any setting. I deliver highly reliable software by practicing test-driven development (TDD) and Continuous Integration and Delivery (CI/CD). Innovative, robust, scalable, reusable, well tested, documented, transferable and on schedule; these are hallmarks of my work.An updated and parsable version of my resume can be found here:https://www.visualcv.com/andrew-c-dearborn__vlsi_softwareProgramming languages and formats: Python, Tcl, Make (Makefile), Perl, SKILL, AutoLISP, C++, Fortran, Java, JavaScript, SQL, bash, csh, HTML, RTL, Verilog, SPF, SPEF, CDL, Spice, XML, JSON, XLSX, CSVTools: Synopsys: ICC, IC Workbench, Lynx, Library Compiler, HSPICE, Primetime, StarRC, Hercules, nettran; Cadence: DFII , CDB, OA, SKILL, PCell, Virtuoso, Layout, Composer, Dracula, Diva; Concept Engineering Starvision, starsh; Mentor Graphics: Calibre, Autodesk: AutoCAD, AutoLISP; Si2: oaScript, PyOA, Liberty Parser; ActiveState: tclchecker; Open Source: Jenkins, Apache, MySQL; HelixCore: Perforce, p4, p4v, py4p4; Enovia (Dassault): DesignSync, dssc; IC Manage: icmp4Operating Systems:Linux: Red Hat Enterprise Linux (RHEL), SUSE, UbuntuMicrosoft Windows: XP, 7, 10Oracle (Sun): Solaris

Listed skills include Eda, Tcl, Circuit Design, Cadence, and 33 others.

Current workplace

Andrew Dearborn's current company

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Tokyo Electron US
Tokyo Electron Us
Principal ASIC Engineer (HPC CAD)
AeroLeads page
9 roles

Andrew Dearborn work experience

A career timeline built from the work history available for this profile.

Principal Asic Engineer (Hpc Cad)

Current

Austin, Tx, Us

Will be leading the development of on site HPC network that will support the hardware engineering efforts of our business division. This will segue into optimization of the current workload balancing system and the flows that will depend on it. This is an incredible opportunity for me as the division is small but profitable, and has the resources and backing of a huge corporation.

Sep 2022 - Present

Senior Staff Cad Engineer

Austin, Tx, Us

As DevOps/IT:Root access across all networks, raising/owning new services, onboarding users, debugging system level errors, qualifying new OS for hardware work flows, installing packages, testing against representative work flows, and working with IT on rollout. Installed/owned these services: * Perforce - Source Control Management* Jenkins - CD/CI and nightly smoke tests* ELK - EDA license analysis* Grafana/Prometheus for license monitoring/notification* IPLM/PiCache - hardware design management* Slurm, Nomad, LSF - job Scheduling* Apache - Web publishing* FlexLM, LM-X - EDA License DaemonsAs CAD Technical Lead:* Compiled and Presented Team status at quarterly design review* Led effort to break up monolithic code base (HW flows, ad hoc tools) into discreet versioned resources* Led effort to adopt an Environment Modules workflow, where ENV settings for tools and services are centralized in modules.* Led effort integrate workload management (Slurm, LSF) into hardware flows. Wrote an abstract job submitter tool (Ruby) that is called via API calls in the flow.* Led effort to implement design management via Methodics IPLM. Installed services, wrote authentication layer (Python3/Pamela against FreeIPA), imported groups from FreeIPA, proposed SCM and workspace organizational models* Led effort to standardize workspaces, making them more collaborative between contractors direct employees in the United States.* Led unit/system testing effort within CAD and other teams* Brought in Concept Starvision to aid in DSPF pruning.* Led effort to qualify the workload manager (Slurm, LSF) via custom profiler. This helped immensely in understanding the performance penalties associated with job guard railing (Cgroups can be costly).* Collaborated with IT migrating Perforce from submit/proxy model to commit/edge model. Wrote Perforce blackbox test suite (Python3)* Manage production Python, Ruby/Rake, and Tcl environments

Jul 2020 - Jul 2022

Senior Staff Cad Engineer

Austin, Tx, Us

Aug 2018 - Jul 2022

Cad Engineer (Front End) - Senior Member Of Technical Staff

Santa Clara, California, Us

Technical Lead on flow and command line tools for merging layout standard cells into PnR and Custom blocks and for netlisting the same. Flows wrapped command line tools inside of Lynx Design System (Synopsys) yielding support for any imaginable use model. Lynx, IC Workbench, Python, Tcl, PyOA (oaScript), pylint, tclcheckerArchitected and developed a platform for aggregating/analyzing top-level routing parasitics for the Stratix 10 device. 43 million D_NETs (with aggressors) extracted, enabling accurate timing modelling, resulting in higher yield and better QoR. Developed load-on-demand parasitic database to minimize time/space complexity; developed algorithms for identifying SPEF errors and aggressors. Tcl, Starvision, Make, PythonLed initiative on how to support early parasitic (SPEF, SPF) deliveries that are often missing/incomplete/dirty, enabling timely feedback, resulting in faster closure. Solely responsible for the checks and flows that became a Design standard for parasitic QA. Starvision, MakeLed initiatives that resulted in dramatic increases in code quality: (1) Developed a flexible and concurrent framework for regression testing applicable to any software project. Discovery and execution of system tests via Makefile; unit testing via unittest/doctest (Python) and tcltest (Tcl). (2) Solely responsible for a multi-language software project scaffold generator, providing base code for project definition, applications, modules, and the concurrent testing framework, automated documentation (Doxygen) and deployment MakefileSolely responsible for creating a Liberty Parser/API that preserved context, enabling applications that could create/modify/merge Liberty files. PythonSolely responsible for a multi-language software project scaffold generator providing base code for project definition, applications, modules, the concurrent testing framework, automated docs (Doxygen) and deployment MakefileAdopted/enhanced some existing in-house C++ tools

Dec 2015 - Mar 2018

Cad Engineer (Front End) - Senior Member Of Technical Staff

Altera

Led effort to introduce the netlist and design database visualization and debugging platform "StarVision" (Concept Engineering) resulting in a productivity boost across the design team. This platform would revolutionize how we solved problems involving any type or mix of netlists.Developed API for pruning hierarchical netlists, which greatly reduced job run time in various domains and simplified the creation of concise test cases. Starvision, Tcl Developed a robust net tracing API with configurable arcs. Starvision, Tcl Led development of a robust Static Connectivity Checks platform that provided textual/graphical debugging and support for test vectors of high complexity. Starvision, Tcl, Excel Developed connectivity quality checks and full chip netlisting for Aria 5 device. Synopsys ICC, TclArchitected and developed a Timing Correlation Framework that managed the submission and correlation of hundreds of parallel Hspice and PrimeTime jobs based on XLSX input. LSF, Python subprocess/threadingDeveloped application/methodology for creating a pruned netlist (Verilog) of a clock network (including side loads), enabling Design to quickly and effectively correlate timing between Primetime and Quartus (FPGA software). Starvision, TclTechnical lead on the Stratix 5 chip assembly platform. Cadence DFII, Layout, Composer, SKILL, IPC

Jan 2011 - Dec 2015

Cad Engineer (Back End) - Member Of Technical Staff

Altera

Architected and developed a chip assembly methodology and tools (Modular Design) that would be standard on 5 technology nodes. The hierarchical tiler assembled the entire device in minutes and dramatically multiplied its value on each family member or engineering change. All placement data were relative; block description files were generated based on schematics, formulas, or manually via shorthand notation. Cadence DFII, SKILL, PerlSolely responsible for the core and visualizer of a robust shape-based DRD (Design Rule Driven) Layout editing platform . The use model was later adopted by Cadence Design Systems after close collaboration. Led or developed all tools. DFII, SKILLSolely responsible for the core and visualizer of a robust shape-based DRD (Design Rule Driven) Layout editing platform . The use model was later adopted by Cadence Design Systems after close collaboration. Led or developed all tools. DFII, SKILLCreated training modules for DRD Layout and SKILL programming and provided multiple weeks-long onsite training sessions for Layout and CAD Engineers at Altera Technology Center in Penang, MalaysiaSolely responsible for creation of a optimizer/placer/auto-router for a routing channel generation flow that reduced Schematic and Layout development time from weeks to seconds. The software would calculate optimal track pattern, shielding requirements, buffer locations/directions, divide long signals, place and route. Perl, DFII, SKILLSolely responsible for a physical net extraction API and de facto "mark net" command in Virtuoso Layout, greatly improving productivity and enabling SKILL based layout extraction for applications. API supported short handling, block/exit conditions, special devices, marker layers and finding shortest path. DFII, SKILLDeveloped abstraction layers to keep Layout applications generic. SKILLWrote simple runsets for Layout verification. Hercules

Sep 1999 - Jan 2011

Senior Layout Designer (Layout/Tapeout Groups)

Altera

Led blocks on various flagship projects and technology nodes of various foundriesIdentified many inefficiencies that I would address as a CAD Engineer.Solely responsible for bringing up Altera's first Intranet web site, supporting web interfaces to various in-house command line tools. Apache, CGI (Perl)Architected a Bonding Diagram generation flow that leveraged the intranet to handle requests, manage lead frame repository, error check, view status; measured productivity increase of >10x due to decreased phone traffic, reduced human error and automation coded inside of AutoCAD. CGI, HTML, JavaScript, Perl, AutoLISPPerformed tape out duties, created layout test frames, reviewed EMIB data

Dec 1995 - Sep 1999

Owner/Consultant/Designer

Quest Web Design

Founded Quest Web Design as an umbrella for all my consulting activities, which included ground-up website design, graphic design and marketing consultation. Provided all technical software and design services; HTML, JavaScript, CGI, Adobe Illustrator and Photoshop.

Jan 1994 - Jul 1997

Internet Connectivity Consultant

Self-Employed

Was de-facto internet connectivity consultant for the campus IT Department scripting for Trumpet Winsock, SLIP, PPP, and PPPoE. Performed installation and configuration of software and drivers for students and faculty in their homes and made hardware recommendations.

Oct 1994 - Dec 1995
3 education records

Andrew Dearborn education

Ba, History / Business

Ucla

Mechanical Engineering

San Francisco State University

Education record

Acalanes High School
FAQ

Frequently asked questions about Andrew Dearborn

Quick answers generated from the profile data available on this page.

What company does Andrew Dearborn work for?

Andrew Dearborn works for Tokyo Electron US.

What is Andrew Dearborn's role at Tokyo Electron US?

Andrew Dearborn is listed as Principal ASIC Engineer (HPC CAD) at Tokyo Electron US.

What is Andrew Dearborn's email address?

AeroLeads has found 1 work email signal at @tel.com for Andrew Dearborn at Tokyo Electron US.

What is Andrew Dearborn's phone number?

AeroLeads has found 2 phone signal(s) with area code 415, 888 for Andrew Dearborn at Tokyo Electron US.

Where is Andrew Dearborn based?

Andrew Dearborn is based in Austin, Texas Metropolitan Area, United States while working with Tokyo Electron US.

What companies has Andrew Dearborn worked for?

Andrew Dearborn has worked for Tokyo Electron Us, Mythic, Intel Corporation, Altera, and Quest Web Design.

How can I contact Andrew Dearborn?

You can use AeroLeads to view verified contact signals for Andrew Dearborn at Tokyo Electron US, including work email, phone, and LinkedIn data when available.

What schools did Andrew Dearborn attend?

Andrew Dearborn holds Ba, History / Business from Ucla.

What skills is Andrew Dearborn known for?

Andrew Dearborn is listed with skills including Eda, Tcl, Circuit Design, Cadence, Cadence Virtuoso, Ic, Asic, and Verilog.

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