• RTL design and microarchitecture development in various CPU units• Manage a small team of design engineers

• RTL design and microarchitecture development in various CPU units• Manage a small team of design engineers

• RTL design and microarchitecture development in various CPU units including load/store, rename, and branch prediction• Collaborate with performance modeling team, perform synthesis trials and other analysis to explore design tradeoffs and guide the microarchitecture specification• Use formal verification techniques to accelerate design checkout and deliver high quality design the first time • Closely collaborate with verification team from design specification through code coverage• Perform static timing analysis, work with physical design engineers to optimize physical implementation• Develop tools to enhance the productivity of the design team

• RTL and microarchitectural design for power management controller in x86-based SOC products.• Closely collaborate with verification engineers and back-end designers. • Design UPF (unified power format) and serve as expert-user on UPF for SOC project.

• Design and verify RTL (SystemVerilog) for FPGAs used in engineering memory tester development• System architecture and board design including component selection, schematic capture, signal integrity and power integrity analysis for development of next-generation engineering memory tester• Co-designed boards such as a board to supply DUT power supplies, board for automatic test pattern generation and capture, and board to post-process captured data from DUT. • Wrote RTL to generate test patterns for DUT, capture and process incoming data from DUT, interface with off-chip memory (SRAM, DRAM, flash), control and measure DUT power supplies. • Designed robust, self-testing and self-calibrating high-speed inter-FPGA interface used widely throughout the system. • Designed RTL to self-test boards during bring-up and manufacture including memory and inter-FPGA interface self-checking.

• Lead probe engineer on top priority, high volume imager. • Developed software for wafer-level testing of CMOS imagers on Teradyne IP750 and in-house tester platform, using C++, Python and Visual Basic • First to implement new testing methods including serial testing and two-pass image capture • Utilized statistical process control and JMP to track yield and process shifts and analyze other metrics • Develop scripts to manipulate and analyze data using Perl

• Developed a system-level application in Java for managing security • Worked on a small, multidisciplinary team focused on delivering high quality software

• Used MATLAB to read and analyze data from machines used for drug discovery and DNA testing • Created MATLAB graphical user interface for interactive analysis and presentation of data results

• Researched a Business Intelligence vendor • Provided competitive and technical analysis of the vendor

• Installed and tested Linux partitions on i5/OS; debugged i5/OS and Linux issues• Received 3 awards from co-workers for contributions to testing