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Design Engineer for next generation MRAM ProductDesign Engineer with 5+ years in 2D/3D NAND Flash memory(2 bit per cell / 3 bit per cell)Specialties• Design Tools: Cadence Custom IC Design Tools(Virtuoso, Logic Equivalence Checking, SOC Encounter, IMC Coverage), Synopsys Design Compiler (PrimeTime, Automatic Place and Route), Cadence NCSim, Verdi Automated Debug System, ModelSim, HDL lint tools (Spyglass), LTspice
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Staff Design EngineerQualcomm Aug 2021 - PresentSan Diego, Ca, Us- Designed digital logic for Secure Processor- Define design spec from architecture proposal- Integrated IPs (MSIP/ Memory....) to Sub System Level- Perform CDC/Lint/Power Check -
Principal Design EngineerSpin Memory Nov 2018 - Jun 2021Fremont, Ca, Us- Designed write/verify algorithm to improve MRAM endurance- Designed logic block to interact with MRAM macro- Designed control logic to interact with CAM array- Created test plans for top level verification using assertion checkers. -
Senior Design EngineerWestern Digital Jan 2017 - Nov 2018San Jose, Ca, Us- Designed logic block to operate with sense amplifier.- Improved performance(timing) for Read and Program operation- Verified data path related circuit and Sense amplifier circuit.- Checked code coverage inside logic blocks Sense amplifier and data path blocks. -
Staff Design EngineerWestern Digital Jul 2017 - Oct 2018San Jose, Ca, Us
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Digital Design Engineer IiSandisk Jan 2013 - Dec 2016Milpitas, Ca, Us- Logic design for 2D/3D NAND flash memory- Designed logic block to control WordLine bias scheme/Address decoder/Erase operation.- Performed full chip verification by verilog in verification environment- Worked on manual ECO(Engineering Order Change) and perform LEC same- Performed verilog netlisting and scripting for post-processing the netlist- Worked on Digital / Analog interface circuit- Performed STA(Static Timing Analysis) using PrimeTime -
Graduate StudentUniversity Of Southern California Aug 2010 - May 2012Los Angeles, Ca, UsGraduate from University of Southern California in May 2012 -
Test Engineering InternStreaming21, Inc Jul 2007 - Aug 2007• Improved existing video on demand software platform and infrastructure• Performed software optimization and unit testings on LINUX
Andy Pai Skills
Andy Pai Education Details
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University Of Southern CaliforniaElectrical And Electronics Engineering -
Chang Gung UniversityElectrical And Electronics Engineering
Frequently Asked Questions about Andy Pai
What company does Andy Pai work for?
Andy Pai works for Qualcomm
What is Andy Pai's role at the current company?
Andy Pai's current role is Staff Design Engineer at Qualcomm.
What is Andy Pai's email address?
Andy Pai's email address is an****@****ory.com
What schools did Andy Pai attend?
Andy Pai attended University Of Southern California, Chang Gung University.
What skills is Andy Pai known for?
Andy Pai has skills like Verilog, Modelsim, Vhdl, C++, Ltspice, Perl, Synopsys Primetime, Linux, Verdi, Digital Circuit Design, Microsoft Office, Ptc Pro/engineer.
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