Andy Cheese Email & Phone Number

Stockholm County, Sweden

Stockholm, Se

Designing and architecting factories of the future through working together with customers and company-internal stakeholders to create factory of the future solutions. I am responsible for the system architecture of Atlas Copco’s industrial automation and manufacturing products that create and deliver customer value. I manage changes to interfaces and functionality together with technical roadmap development. I also work together with product marketing and management to construct and refine product requirements and produce customer-specific solutions.

Stockholm, Se

Job Title : Software Development Manager/Systems ArchitectI was the manager (line, project - Agile/Scrum - and technical) of the risk engineering software development group and was responsible for the real-time purchase flow, credit and fraud assessment, and payment software within the Klarna e-commerce payment solution. I was responsible for all line activities including recruitment, salaries, budget management, personnel development, motivation, 24 hour on-call support, and time reporting.Job Title : Systems ArchitectSystems Architect for real-time domain including complete purchase flow, interfaces to merchants, identification of returning customers, authentication of returning customers, credit and fraud assessment, and payments. Responsible for architecture and system design for Merchant Onboarding solution for migrating existing Ebay Tradera estore merchants to Klarna and onboarding new estore merchants. I also worked together with stakeholders and vendors to select third party software to use within Klarna’s solutions.

Shenzhen, Guangdong, Cn

Chief System and Software Architect for Infrastructure as a Service (IaaS) virtualisation platform for applications such as Cloud Computing and High Availability Servers. The IaaS platform architecture has been adopted as the basis for the next generation Huawei Core Network systems and the Huawei company-wide software platform.System Architect for Content Delivery Network Platform.Patent in the area of IaaS/Virtualisation/Cloud Computing for platform support for highly available applications; US20150113149 "Method and Apparatus for Allocating Resources".Filed DMTF proposal in the area of IaaS/Virtualisation/Cloud Computing platform support for highly available applications.Focus areas include virtualization technology, and Multi and Many Core operating systems and microprocessors and related software technology (imperative and declarative programming languages).

Kista, Stockholm, Se

Job Title : Platform System/Software Architect for Multimedia Mobile Phone Clients (2007–2009)Responsible for System Architecture of Terminals and Clients across Ericsson’s multimedia product portfolio. Terminal architectures include mobile phones, PCs, and Set-Top Boxes. Microprocessor architectures include ARM and Intel x86.Responsibilities included system/software architecture definition of Ericsson’s multimedia client platform, which is a common backend for parallel execution of IMS and non-IMS clients. In addition, being responsible for the client system architecture for Ericsson/Sony Ericsson’s Rich Communication Suite client, RCS.Job Title : Platform System Architect Radio Network Controller (RNC) (2004–2007)Member of platform system architecture group for the 3G WCDMA mobile networks RNC node. Responsible for software architecture, writing requirements, analyzing requirements, composing implementation sketches and proposals. The platform software is written in a mixture of UML (RoseRT), Java, C++, C and assembler.Responsible for areas such as user-plane packet data processing (Iu-PS) over Ethernet, user-plane data (Iu-CS. Iu-CS, and Iub) optimization and hardware acceleration, UML model implementation on Multicore processors, support for Kasumi encryption, management of physical memory and stable storage resources, system parameters and licensing to simplify product handling to have a single software version to run on all RNC node types, robustness and availability.Job Title : Platform System and Software Architect (2001–2004)Member of Operating Systems/Platform (Enea OSE, Linux, PowerPC) department. The platforms are used by all Ericsson’s LTE and WCDMA nodes including Radio Base Stations, Radio Network Controllers and Media Gateways. Platforms are constructed around the OSE operating system and PowerPC microprocessors. Leading teams of up to ten people working on system and software architecture assignments.

Geneva, Switzerland, Ch

Manager (Line, Project, and Technical) of Operating Systems Development Group split between the UK and Italy.Overall responsibility for the technical direction and management of projects and lead programmer/architect on projects.Technical management of operating systems/device driver/platform projects and the system architecture of advanced multiprocessor Digital TV set-top boxes.Technical management of a joint project with Sun Microsystems producing JavaOS for ST/Hitachi SH4 microprocessors.Technical management of ports of Unixware/MK and Chorus/ClassiX operating systems to the STMicroelectronics’ Chameleon microprocessor family. Unixware/MK was the microkernel version of Unix System V Release 4 produced by the Amadeus industrial consortium (Unisys, ICL, STMicroelectronics, Siemens, Unix System Laboratories, Fujitsu).Technical management of participation to the OMI Ouverture – European Commission ESPRIT Project6603.The target system for the Unixware/MK port was an Intel 486 PC platform containing an ASIC implementation of the Chameleon microprocessor.The target system for the Chorus/ClassiX port was a multiprocessor multithreaded/multicore Chameleon multimedia Digital TV set-top box.Contributions to the Unixware/MK port include design and development of the bootstrap, process management subsystem and virtual memory management.Design of virtual memory management for port of Unixware/MK to Non-Uniform Memory Architecture (NUMA) multiprocessor platforms (OMI Ouverture – European Commission ESPRIT Project 6603).Contributions to the Chorus/ClassiX port include virtual memory management, enhancements to support real-time multimedia functionality of Chameleon microprocessor familyResponsible for group software engineering activities, in particular for CMM level 2 certification, progressing towards CMM level 3 and also responsible for the group passing regular ISO 9001 audits.

Leading a team of five people working on operating system engineering assignments for ACRI multiprocessor server supercomputer.Design of DEC OSF/1 Unix binary compatibility for ACRI operating system.Design of file system/virtual memory buffer cache management for multiple page size support for DEC OSF/1 Unix.Design and implementation of a kernel debugger for DEC OSF/1 Unix.

Munich, De

Operating Systems :Port of Unix System V Release 4 ES/MP (also known as SVR4.2MP and Unixware1) (Intel x86 Reference Port technology) to multiprocessor MIPS R4400 Multibus I and II system.Responsible for process management subsystem and related code : context definition, context switching, exception and interrupt handling, clock interrupt handling, dynamic loader, ELF loader, signal handling, ps command, kernel core dump and kernel debugger, procfs process filesystem, processor filesystem and kernel startup and initialisation.Development of a device driver for EISA-based SCSI RAID disk array controller. Port and parallelisation of Unix System V Release 4 to a multiprocessor Intel 486, Multibus I and II system.Responsible for boot and kernel startup, kernel initialisation, trap and interrupt handling, system timer driver, drivers for system bus interface chips, parallelised real-time clock driver, multiprocessor kernel debugger, I/O debugging tools, and lock debugging tools.Performance analysis of the Mach 2.5, OSF/1, and the microkernel-based Mach3 and Chorus operating systems.Developed pseudo device driver for monitoring and performance analysis of Unix and Unix-like operating system kernels.Preliminary port of the Mach3 microkernel for Siemens Transdata telecommunication switch project. This included the design and development of an OSF/1 compatible Streams server supporting the porting of existing Streams modules such as TCP/IP and HDLC (including a short sabbatical at OSF Research Institute, Grenoble).Represented Siemens on the POSIX Pthreads standard working group.Distributed Systems :Design of a distributed systems services platform (HARNESS, European Distributed Systems Integration Project – European Commission ESPRIT Project 5279).

Operating Systems :Specification of operating system requirements for functional and logic programming language systems for parallel/multiprocessor computers.Porting of the Microkernel-based Mach 2.5 operating system to a distributed system environment (network of workstations) project including adding NFS 4.0 for diskless client support, and designing a distributed virtual memory system for a network of Sun Microsystems client workstations and servers.Programming Language Implementation :Design and implementation of a computational model for the parallel execution of Prolog (European Declarative Systems – European Commission ESPRIT Project 2025).Ported ECRC parallel Prolog system to Sequent Symmetry multiprocessor (Intel x86) computer.Design and implementation of a parallel constraint programming system.

Phd, Computer Science

Msc, Computer Science

Bsc, Mathematics With Computing

Education record