Angel Alvarez Ruiz Email & Phone Number

Valencia, España

Working into a great team responsible for industry-leading Integrated Circuits targeting next-gen Wireless Communications. Involved in chip/subsystem architecture, digital design, integration, initial verification, FPGA prototyping, bringing the chip to production and post silicon validation.

Worked on parallel programming and code acceleration (offloading) in heterogeneous platforms which combine CPUs with accelerators such as GPUs and FPGAs. This European Research Project (FitOptiVis) involved some industrial partners, such as Philips, Nokia and Thales Alenia Space.

Code performance analysis (BER/CER) through C/MATLAB models and hardware implementation of a Non-Binary LDPC decoder for space applications using VHDL. The design was particularized for a space-certified Virtex-5QV FPGA and highly area-optimized.

HW-SW co-design for acceleration of C++ and OpenCV based video processing applications. The hardware was designed using high-level synthesis (HLS) and integrated in a Linux system over the Xilinx Zynq SoC platform, leading to an effective speed-up of the target application.

Master Of Science, Telecommunication Engineering

Final thesis: "VLSI Architecture and Implementation of a Non-Binary LDPC Decoder for Space Telecommand (TC) Links"

Bachelor'S Degree, Telecommunication Engineering

Specialization in Electronic Systems Final thesis: "Hardware-Software Co-design of a Positioning System Based on Video Processing"