Staff Engineer, Doe Owner
Current- Design of Experiment Owner: definition for VLSI process characterization (systematic, defectivity and performance variability) for bulk, FinFET, and nanosheets technologies.- Co-inventor of several test structures for defectivity and parametric testing (digital, analog and SRAM devices)- Process and device simulations with Synopsis Sentaurus TCAD, investigation on LLE in FinFET devices- Automatic design flow development- Client management- Project Manager- IC layout design: PDF CV™ test chip design and verification for most advanced technologies (Bulk, SOI, FIN FET, FDSOI, Nano-Tubes, Nano-Sheets)- Yield Ramp for 90/65/45/32/28/22/20/14/10/7/5/2 nm Technology Nodes- Technology Development for 22/20nm, 14nm, 10nm, 7nm, 5nm, 2nm- SRAM defectivity characterization: Design of Experiment- Device Performance Variability Characterization: Design of Experiment- Design for manufacturability- Design of VLSI layer misalign and aging sensors- Investigation of performance variability due to Local Layout Effects related to lithography, contamination and mechanical stress