Anik Balo Email & Phone Number

Dhaka, Bangladesh

Dhaka, Bangladesh

• Implemented ASIC designs using muti-power domain and body bias to achieve higher clock frequency and optimum PPA.
• Implemented STA ECOs to close the timing of timing critical ASIC designs.
• Prepared bash scripts for timing report parsing and generating summary in the context of slew, fanout, load, delay, wire routing layer, and length.

Dhaka, Bangladesh

• Trained and managed newly recruited design engineers in OpenROAD flow for the “OpenROAD 7nm Design Contest” and one of them won in the best PPA category.
• Performed synthesis to GDSII of timing critical designs and closed the timing by following several techniques.
• Analyze the clock tree, skew, and slew. Reduced timing violations by setting optimum slew, skew, and useful skew.
• Analyzed the power and EMIR of designs in both static mode and dynamic mode using RedHawk and Cadence Joules signoff tools and resolved the hotspot area.
• Prepared custom TCL scripts to save the overall design time cycle while analyzing the designs.

Dhaka, Bangladesh

• Responsible for synthesis to post route of several designs and fixing the signoff timing and DRC checks.
• Worked with the physical design flow development team on MMMC generation scripts, custom steps scripts, directory structure, and version control using TCL, Bash, Python and Git.

Dhaka, Bangladesh

• Got industry-oriented training on scripting language TCL, Bash and performed report parsing.
• Got detailed training on Cadence based RTL to GDS PD flow.
• Performed synthesis to GDS of different designs using 45nm and 64nm PDKs.

Dhaka, Bangladesh

• Assisted faculty members in the making of course contents and outlines, make-up class schedules, and the collection of assignments.
• Prepared seat plans for 100-plus students for the examinations and assisted faculty members in proctoring examinations.
• Mentored 100-plus students by attending classes, reviewing materials, and taking notes to help them understand the topics during visiting hours.
• Guided students in the lab to complete experiments by demonstrating Silvaco Athena Process simulations, Circuit, and layout design in Microwind, and Matlab in digital signal processing lab.
• Helped faculty members with record keeping, such as tracking attendance and reviewing lab reports/assignments.