With over two decades of expertise in managing various aspects of silicon IP & Library CAD design including block level implementation, Modelling, Simulation, EDA View Generation, CAD Tools Methodology & flows, encompassing a wide range of Foundation, AMS and Third-party IPs to enable SoC implementation and sign-off.Extensive experience in driving IP and Library Design stakeholders mainly Process PDKs team, CAD Flows, SoC divisions, Automation and EDA partners/vendors to define and enable IP-SoC integration, implementation and Signoff across a variety of technology nodes (FF, CMOS, eNVM, BCD..).More than a decade of experience in leading large engineering teams, managing resources, and cultivating customer relationships.Authored numerous technical papers and holds a patent on DDR2 IO-Memory Interface.