Anjui Shey Email & Phone Number

Beijing, Cn

Austin, Texas, Us

* Architect integrated design solutions development and design closure methodology support for microprocessor design. Drive the following tools/flows development: Noizilla (gate-level functional noise analyzer), Tranzilla (transistor-level functional noise analyzer for digital and AMS design), Oyster-SI (gate-level SI-aware static timer), TLT-SI (transistor-level SI-aware static timer), SpiceX (STA-Spice correlation and sign-off tool with full aggressor paths and variation models support for post-silicon correlation/debug), Gladius (automatic transistor-level timing-sensitive circuit extraction and modeling tool to accelerate what-if analysis), AMP (physical design by tiling leafcells and parasitics model extraction for memory array), StatEngine (simplifying variation analysis of critical timing paths through the application of Machine Learning)* Developed and delivered system SI/PI validation tool suite: ISST (Object-oriented MatLab based system simulation tool for high-speed link system design), DIALOG (Event-driven analog and mixed signal verification platform for SerDes application based on DPI-C & SystemVerilog) * Lead development of design methodologies and design flows based on vendor tools for timing, SI, and noise sign-off analysis and verification. Also provide expert user-level application support on EDA vendor tools (ex. PrimeTime-SI, StarRC, XA, HSPICE, Virtuoso, Spectre, IC Compiler, Calibre, …) for timing and physical design closure* The methodologies and design solution suite have been deployed for successful tape-outs of more than 10 advanced microprocessor chips and bring-up of serial link with data rate performance meeting requirements of 25Gbps

* Led product development of µArch, a comprehensive micro-architecture design creation and analysis platform for SoC design and verification of nanometer integrated circuits. µArch uses a propriety design entry technology for higher abstract design than RTL, a high-level synthesis engine to provide automatic control logic generation, and a simulation driven verification engine to verify the generated RTL code and debug the module specifications.

Us

* Key contributor to design of the core engine and application features of a circuit analyzer based on hybrid approach (Dynamic Simulation + Static Analysis). Designed and implemented concurrent hybrid signal state propagation flow (DC and transient), clock tree recognition and simulation, automatic false signal detection and elimination, critical path tracing, model extraction, and automatic timing verification covering combinational cell, gated clock, and dynamic logic. * Designed new features in a full path timing sign-off tool, CRITIC to simulate clock trees and critical paths in post-layout synthesis-driven designs, to accurately incorporate miller effects in circuit simulation and devised new dynamic current injection mechanism to simulate the worst-case crosstalk effects without iterations.

Sunnyvale, California, Us

* Provided technical leadership and vision in defining full-chip noise-aware timing verification products/flow. Managed an R&D group for the development of core technology for new generation of static timing analysis/verification tools with dynamic simulation extension and various model abstraction capabilities. * Key contributor to PathMill (NanoTime), a mixed transistor level and cell level static timing analysis and verification tool. Responsible for development and implementation of core algorithm and application features, as well as maintenance and customer support. Served as a technical liaison with key customers(ex. Intel, IBM, AMD, ...)* Coordinated the PathMill product release cycle through three major releases. Led integration effort of PathMill and PrimeTime for SoC noise-aware timing solutions.