Anjui Shey Email and Phone Number
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Anjui Shey personal email
An innovative, hands-on engineering leader with extensive experience in research and development of custom design solutions and methodologies for processor, memory, analog & mixed-signal (AMS) circuit and high-speed link system design. Strong skills in statistical analysis and project management. * Programming: C/C++, Perl, TCL, Java, Python, SKILL, Shell scripts, MatLab, Veirlog, SystemVerilog, Verilog-AMS, SQL, Object-oriented programming, Parallel programming, Subversion, Make* Design tools: HSPICE, XA, Spectre, SmartSpice, Virtuoso, VCS, Design Compiler, IC Compiler, Calibre, PrimeTime, NanoTime, StarRC, ADS, CST, HFSS, Sigrity, Allegro, JMP, VNA, TDS, PDK, MySQL* Specialized skills: Static timing and noise analysis, Circuit simulation, Variation analysis, Power & EMIR analysis, AMS functional verification, Signal Integrity, Power Integrity, Timing & Physical design closure, High-speed link system design, modeling & simulation, High-speed board P&R, Application of Machine Learning in design tools and methodologies
Empyrean Technology
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Senior Application EngineerEmpyrean Technology Apr 2018 - PresentBeijing, Cn
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Senior Principal Engineer/Senior ManagerOracle Nov 2004 - Oct 2017Austin, Texas, Us* Architect integrated design solutions development and design closure methodology support for microprocessor design. Drive the following tools/flows development: Noizilla (gate-level functional noise analyzer), Tranzilla (transistor-level functional noise analyzer for digital and AMS design), Oyster-SI (gate-level SI-aware static timer), TLT-SI (transistor-level SI-aware static timer), SpiceX (STA-Spice correlation and sign-off tool with full aggressor paths and variation models support for post-silicon correlation/debug), Gladius (automatic transistor-level timing-sensitive circuit extraction and modeling tool to accelerate what-if analysis), AMP (physical design by tiling leafcells and parasitics model extraction for memory array), StatEngine (simplifying variation analysis of critical timing paths through the application of Machine Learning)* Developed and delivered system SI/PI validation tool suite: ISST (Object-oriented MatLab based system simulation tool for high-speed link system design), DIALOG (Event-driven analog and mixed signal verification platform for SerDes application based on DPI-C & SystemVerilog) * Lead development of design methodologies and design flows based on vendor tools for timing, SI, and noise sign-off analysis and verification. Also provide expert user-level application support on EDA vendor tools (ex. PrimeTime-SI, StarRC, XA, HSPICE, Virtuoso, Spectre, IC Compiler, Calibre, …) for timing and physical design closure* The methodologies and design solution suite have been deployed for successful tape-outs of more than 10 advanced microprocessor chips and bring-up of serial link with data rate performance meeting requirements of 25Gbps -
PartnerArchi Design Automation Jun 2003 - Oct 2004* Led product development of µArch, a comprehensive micro-architecture design creation and analysis platform for SoC design and verification of nanometer integrated circuits. µArch uses a propriety design entry technology for higher abstract design than RTL, a high-level synthesis engine to provide automatic control logic generation, and a simulation driven verification engine to verify the generated RTL code and debug the module specifications.
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Principal Software EngineerNassda Jan 2000 - May 2003Us* Key contributor to design of the core engine and application features of a circuit analyzer based on hybrid approach (Dynamic Simulation + Static Analysis). Designed and implemented concurrent hybrid signal state propagation flow (DC and transient), clock tree recognition and simulation, automatic false signal detection and elimination, critical path tracing, model extraction, and automatic timing verification covering combinational cell, gated clock, and dynamic logic. * Designed new features in a full path timing sign-off tool, CRITIC to simulate clock trees and critical paths in post-layout synthesis-driven designs, to accurately incorporate miller effects in circuit simulation and devised new dynamic current injection mechanism to simulate the worst-case crosstalk effects without iterations. -
Principal Developer/R&D Manager, Primetime TeamSynopsys Inc Dec 1995 - Jan 2000Sunnyvale, California, Us* Provided technical leadership and vision in defining full-chip noise-aware timing verification products/flow. Managed an R&D group for the development of core technology for new generation of static timing analysis/verification tools with dynamic simulation extension and various model abstraction capabilities. * Key contributor to PathMill (NanoTime), a mixed transistor level and cell level static timing analysis and verification tool. Responsible for development and implementation of core algorithm and application features, as well as maintenance and customer support. Served as a technical liaison with key customers(ex. Intel, IBM, AMD, ...)* Coordinated the PathMill product release cycle through three major releases. Led integration effort of PathMill and PrimeTime for SoC noise-aware timing solutions.
Anjui Shey Skills
Anjui Shey Education Details
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Uc San DiegoElectrical And Computer Engineering
Frequently Asked Questions about Anjui Shey
What company does Anjui Shey work for?
Anjui Shey works for Empyrean Technology
What is Anjui Shey's role at the current company?
Anjui Shey's current role is Custom EDA/CAD Solution, Design Methodology/Flow, Timing & Physical Design Closure.
What is Anjui Shey's email address?
Anjui Shey's email address is an****@****sun.com
What schools did Anjui Shey attend?
Anjui Shey attended Uc San Diego.
What skills is Anjui Shey known for?
Anjui Shey has skills like C++, C, Verilog, Debugging, Cloud Computing, Application Specific Integrated Circuits, Vmware, Vmware Fusion, Vmware Infrastructure, Virtualization.
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