RTL Design Engineer with 3 yrs. of experience in CPU design. Involved in building high-performance RISC-V core, including design and validation of Debug and Trace extensions, managing pipeline tasks such as stall and flush controls, and optimizing pipeline efficiency. Gained a good understanding of HDLs like Verilog and SystemVerilog, as well as key design considerations like power, performance and area. I'm passionate about semiconductor industry and enthusiastic about contributing my knowledge while also continuously learning and expanding my expertise.