Development of platform for POS terminals.Worked on the software platform of touch-screen POS terminals. Worked on core services running on the terminal (secure transactions, UI, communication etc). Worked on bug fixes and feature enhancements both in proprietary version of AOSP (Android Open Source Project) and in C kernel.Testing was being done by creating Android applications, creating Python tests for them and integrating in the Jenkins automation system.

Development of a Verilog design parser/analyzer.Implemented a software which was parsing verilog code and creating the required database and the graph of the design elements. It was also running algorithms on the graph to analyze some properties of the design. Also was generating XML database for the design.

Development of embedded software for POS terminals.Worked on the software platform of POS terminals. Implemented core services running on the terminal, including secure services (related to cards, secure transactions etc), UI and telecommunication services. Created corresponding libs/APIs for terminal applications. Event driven programming was used.The verification was done by creating test applications running on the terminal. The tests were implemented on Python.Used mocking/stubbing mechanism for unit testing.

Worked on the development of the Placement flow of FPGA compiler. Worked on local placement corrections in order to fix placement violations and optimize timing before starting Routing phase.Development of various design checkers for Placement and Routing flows of FPGA compiler (placement correctness checkers, clock assignment checkers, connectivity checkers etc.).

Software development, QA, team leading, junior training.Spheres: EDA, ESL, RTL design, Android/embedded, Image processing, GPGPU/parallel programming. EDA/ESL/RTL design sphere: Development of design checkers for Placement flow of FPGA compiler. QA of a specific FPGA tool-chain. Created verification suites with the documentations. The tests were being implemented in Verilog/VHDL. Included verification on the real device (JTAG used). Verification suites for: FPGA clocking tree validation, FPGA Design Library macros verification, interactive Hardware debugging tool: (front-end (instrumentation features) and back-end (hardware debugging capabilities) verification), Static Timing Analysis engine, coverage suite for synthesizable subset of Verilog and VHDL languages for a Synthesis tool. FPGA tool chain verification using large and real designs (communication, multimedia, DSP). Development of the test harness for RTL to bit-stream tool chain validation. Modeled bridges between protocols: AHB, AXI, OCP. Used a high level synthesis tool. Implemented in System Verilog with extensions. Prepared appropriate documentation. Worked as a Team lead. Design, implementation and optimization(parallelization/pipelining) of DSP algorithms for massively parallel device.Android/Embedded: Development of an Android application for the online catalog repository.Image processing: Development of Jpeg to/from BMP converter. Development of Super Resolution Video algorithms.GPGPU/Parallel programming: Development of a C++ reference applications and acceleration with parallelization using NVIDIA CUDA and ATI Stream platforms. A multimedia system with data encode/decode: routing/processing inputs from multiple streams of different types (H.264 and YUV stream), compositing of multiple streams into a single output. A financial forecasting framework.

Design, implementation and optimization (parallelization, pipelining) of DSP algorithms for the customer's massively parallel processing device:1) implementation using customer's proprietary language2) reference implementation in C/C++ (also using Matlab/Octave)3) test suite implementation4) white papers creation on design/implementation flow

Worked on the development of a QA management tool.