• Leads test program qualifications both in-house and subcon sites of Versatest (Turbo C) and Nextest (C++) on Block-Based Test Methodology (BBTM) for Programmable System on Chip (PSoC: mixed signal) devices• Drives quality for test programs by ensuring the limits are within Datasheet, implementing required tester guardbands and if necessary correlating or characterizing on bench set-up• Initiates test time reductions on programs to improve total test cycle time• Leads device/package qualifications, characterizations, data analysis, test programs and yield enhancements of different Cypress products (USB and SRAMs) with minimum management input• Drives “Zero Defects”, quality enhancement initiatives, SPC, DOE, continuous improvement, 8D, QA and FA corrective actions, and provides resolutions including RMA’s and other customer driven quality actions• Collaborates with product engineers at Backend and Sort (Wafer Fabs) to attain needed test program/flow coverage• Spearheads backend flow construction, platform migrations, vendor and subcon qualifications and breaks through any barrier during the execution• Implements Hidden Row Data Base (HRDB) program loading on Versatest and Nextest as Quality Initiative for Programmable Devices• Follows and contributes on best practices specs in test program development and release• Uses Subversion tool in maintaining test programs for easy history tracking and integration of changes from other test engineers• Collaborates with Assembly/Packaging Engineers at Back-end, Test and Product Engineers at Sort (Wafer Fabs), Applications Engineers and Design Engineers in defining manufacturing plans• Independently schedules short term goals with demonstrated accuracy and assists with definition of long-term project goals• Evaluates methods and establishes Best Practices for product release to manufacturing