Anne Meixner Email & Phone Number

Portland, Or, Us

The Engineers' Daughter LLC: Applying Expertise to Client's Semiconductor and Electronics Test challenges and Applying Engineering Experience to Development of EngineersTest Technologist, Training and Technical Leader servicesSemiconductor Test Manufacturing and DFT expertiseWorkshops for technology workers for career developmentStarting a social media platform to connect people early in their careers with people practicing their profession.Website www.engineersdaughter.org to launched in March 2016.Looking for engineers to write stories.

Teaching Beginners through Intermediate Adults and Children Alpine Skiing. Customer Service to resort guests.

Santa Clara, California, Us

21+ years as a test technologist focused on mixed-signal and analog test methods. Effectively proved new test methods which impact manufacturing test with empirical data and drove adoption via presentations, documentation and training. Successfully applies collaboration skills- connecting people and connecting knowledge across engineering teams. Proven skills working on and leading cross-functional teams.Key Methodologies and Technologies:Converged unit selection methodology for silicon validation to assure that units representative of manufacturing process variation were identified and delivered to engineering teams.Directed pathfinding work for tracking IP manufacturing performance for SoC products. Proof of Concept and pilots highlighted capabilities and pointed out weaknesses.Lead an engineering team focused on IO DFT, test methods and board design with goal of simpler load board designs for manufacturing test.Created Oregon Technical Leadership Forum which shared tips and ideas on technical leadership at the Oregon Intel Campus.Directed a 4 year PLL DFX research collaboration between Intel engineers and academic research group from University of Mass at Lowell.High Speed IO DFT and Test Methodology development, scope included USB 2.0, S-ATA, PCI Express, FBD, QPI.Led development of two courses for Intel IO DFT Based Test methods.Validated pre-silicon and post-silicon AC IO Loopback (aka Timing Margin) on a P858 microprocessor, Willamette. Eliminated need for high precision timing accuracy pin electronics Technology continues to be used on single-ended interfaces, i.e. DDR2/3.Designed a weak write test mode circuit and proved that this test method effectively replaced a 1 second data retention test.3 US patents.12 externally published papers/posters

Armonk, New York, Ny, Us

Worked for the Product Assurance Organziation.Executed quals on gate array technologyRan empirical study for the first Weighted Random Pattern testing on a logic product.I credit my work at IBM for getting me interested in test.Worked on Masters in the evening.Took an educational leave of absence in August 1988 to pursue further graduate studies

Ph.D., Electrical And Computer Engineering

Msee, Electrical Engineering

Bsee, Electrical Engineering