ntel Digital Enterprise Group/Intel communication Group/Intel Wireless Group?Worked on Intel first 64bit microprocessor (Itanium(@)).* Involved in the tape out of Intel high speed IO FSB's protocol chipdevelopment.* Intel iXP-425 network processor.* Sram compiler for Intel first DSP chip (Frio@).Skillset: Digital design, analog design, validation, mixed signal, SOC, toolautomation.

Freescale/NXP/Wipro IncSr. Architect. Serdes IP Verification Lead and mixed signal designerLed pre-silicon verification team on Serdes IP development. Responsibilitiesinclude:? Deliver Serdes IP architecture verification plan and execution.? Define and implement logic verification flow methodology by system-verilogand UVM.? Define mixed signal verification methodology and test plan. Execute analogand digital closed loop verification simulation, such as PLL, DCC, TX and RXequalization.? RTL logic implementation such as control state machine and analog cellmodeling with both wreal and digital techniques.? Gate level verification and RTL sign off checkers. (e.g. CDC, HAL, LEC and etc).? STA, synthesize and SOC and Post-silicon debug supporting.? Design automation, Fluent in C-shell, Matlab, Perl and Python.Involved multiple generation of Serdes IP (5G, 10G and 28G) mixed signaldesign and validation. Deep knowledge in High speed IO architecture andcritical issues.