Annika Lee Email & Phone Number

Cupertino, California, US

Santa Clara, California, US

• Led silicon HW teams in project execution, covering RTL, DV, DFx, PD, Timing, Power & reliability, and successfully delivered committed POR projects.
• Enhanced the Project Management processes, tools, and methodologies, including 33% increased efficiency in bug tracking and minimizing bug counts, showcasing robust tracking and reporting capabilities.
• Initiated quality checks consolidation into a centralized source, integrating pertinent data to uphold quality standards, resulting in a 20% boost in engineering team productivity.
• Revitalized the project BOM with a hierarchical structure mirroring engineering implementation, significantly improved license accuracy and visibility, optimizing maintenance processes.
• Experience in leading programs from new product introduction, along with tools, flows, methodology planning, and readiness, to driving schedules, milestone interlocks, and SOC execution from concept to production.
• Technical program management expertise in complex SOCs, encompassing next-gen FPGA, high-performance IO, Transceiver, ARM subsystems, DDR, Fabric, and processors.

Fremont, California, US

• Led cross-functional teams across Engineering, Account Manager, Purchasing, Production, QA, CM, and OEM/ODM vendors throughout the project development life cycle from concept to mass production.
• Designed, proposed, and promoted system integration projects to resolve current and potential customer issues, including cost reduction, architectural improvement, entering new market sectors, and system failure risk..
• Led the delivery schedule of product for the development phases, hardware and firmware testing and validation schedules, and ensured the quality and qualification to meet mass production timelines. Provided support for.
• Hands-on validated and debugged customer issues related to BIOS setting, EC programming, and other on-board connections and configuration problems. Guided NPI engineers in functional tests, temporary work-around, and.
• Drove multi-functional and vendor failure/root cause analysis, and implemented correct action measures. Drove suppliers and integrated their work and schedules into the development process.
• Communicated status and technical concept the executive leadership and business leaders.

San Jose, CA, US

• Designed and verified pre-silicon functional blocks for switch and router using Verilog and SystemVerilog languages. Responsibilities include implementation of RTL design changes and enhancement, test-plans and tests.
• Created scripts to post-process regression results and customize passing criteria based on functional needs. This reduced the regression run time by 20%, and is scalable from block level to system level.
• Improved team productivity by creating several scripts to automate verification processes during multiple-project development phases. Automation scripts had at least pulled in one man month in schedule, and were widely.
• Drove & tracked cross-functional design teams, such as backend/PD team and external vendor, to debug and identify issues that may block the progress and ensure the quality and timely delivery.Led & project-managed ASIC.
• Drove & program-managed technical training within ASIC design and verification team. The goal is to support the engineers to keep up-to-date on the latest technology and methodology for continuous education at work..
• Led & program-managed regular Cisco Visit for overseas high school students twice yearly. Defined attendee requirements, event content and schedules, and overall expectations of the Cisco Visits. Presented and planned.

Santa Clara, California, US

• Led & project-managed multi-functional IP teams in ASIC design. Developed and tracked project tasks, schedules, milestones, and deliverables throughout project implementation phase in front-end design and verification.
• Implemented project-management methodology using excel to include detailed status tracking and report, identified potential issues and bottleneck, and presented to management.
• Designed & validated multiple chipset components from pre-silicon design concept to post-silicon bringup. Component ownership includes EC, ILA, ACPI, LPC, memory controller, reset sequence design to meet MS AOAC.
• Developed FPGA & bring up environment and test-plan based on design specifications. Tests are developed in firmware-like C/C++ languages to verify the signal integrity and IP functionality & reliability. Executed FPGA.

Santa Clara, California, US

• Designed and validated multiple chipset components using Verilog and SystemVerilog languages. Component ownership includes PLL modeling, clock gating logic, and PCI-Express interfaces with display, graphics, memory.
• Developed high performance simulation methodologies including test plan & code reconstruction, checker & tracker development, and coverage point identification for validation & debug.
• Validated power consumption using Watermark and analyzed & constructed data results.

• Designed and constructed several programs to perform pixel matching & data analysis for digital image processing using Matlab in 3D Holographic Archie Memory system research project. Programs performed image recovery.

Ms, Electrical Engineer

Certificate, Advanced Project Management

Bachelor Of Science - Bs, Electrical And Electronics Engineering