•Worked on an ongoing project based on All Digital Upconversion of RF signals.•Verified readings from Integrated Logic Analyzer.•Debugged the no-clock warning and clock domain crossing timing error using Phase Locked Loop clocks.•Identified and resolved mismatches in Fast Fourier Transform output, improving simulation accuracy by 12.5%.•Automated the process of analyzing large data sets using MATLAB.•Performed constant refactoring of MATLAB scripts and Vivado configurations to improve code quality and maintainability.