ASIC (Front-End) & FPGA Design and Verification for LiDAR datapath processing, using SystemVerilog, with a focus on Functional Safety in compliance with ISO26262 and ASPICE processes.Utilize Synopsys VC Spyglass Lint and CDC tools in support of high QoR design.Support Design Assurance by performing FPGA Design Code Peer Reviews via Github.Design and test firmware written in C for ARM-based MCU.Driving creation and maturity of FPGA development process towards ASPICE and ISO26262 Compliance.Perform hands-on debugging on hardware using FPGA and processor debugger tools.Support bring-up of new hardware through custom FPGA builds, establish test criteria forinterfaces and sensors.Established and Implemented code coverage regression methodology using Synopsys Verdi

• Responsible for ASIC (Front End) & FPGA design and verification using SystemVerilogand Universal Verification Methodology (UVM)• Experience with designing for Intel 22nm ASIC node.• Experience with using Xilinx High Level Synthesis (HLS) for implementing imageprocessing functions• Experience with current generation FPGA devices: Zynq SoC, Virtex 7, Ultrascale+• Extensive debugging experience with Xilinx Hardware Manager, and Vitis/SDK• Experience with TCL and shell scripting in support of automated FPGA build flows• Experience with integrating in the lab with software, systems, and test engineers on aHardware-in-the-Loop setup• Responsible for creation of Design and Verification specifications• Support Design Assurance Department by performing FPGA Design Reviews• Utilize Real Intent’s Lint and Meridian CDC tools in support of high QoR designs• Experience with configuration management systems: Gitlab with CI/CD for FPGA/ASIC design, Razor, AccuRev,Git, Jira• Experience with Anti-Tamper applications/implementations and associated Validation &Verification process and execution• Support multiple Failure Review Boards (FRB’s) in a production environment to determineroot cause of failures so that production line meets contractual requirements• Provide on-boarding to newly hired engineers to ensure assimilation with Lockheed MartinFPGA design and verification process

• Responsible for FPGA design and verification using SystemVerilog and Universal Verification Methodology (UVM)• Experience with using Xilinx High Level Synthesis (HLS) for implementing image processing functions• Experience with current generation FPGA devices: Zynq SoC, Virtex 7, Ultrascale• Extensive debugging experience with Xilinx Hardware Manager, and SDK• Experience with TCL and shell scripting in support of automated FPGA build flows• Experience with integrating in the lab with software, systems, and test engineers on a Hardware-in-the-Loop setup• Responsible for creation of Design and Verification specifications• Support Design Assurance Department by performing FPGA Design Reviews• Utilize Real Intent’s Lint and Meridian CDC tools in support of high QoR designs• Experience with configuration management systems: Razor, AccuRev, Git, Jira• Experience with Anti-Tamper applications/implementations and associated Validation & Verification process and execution• Support multiple Failure Review Boards (FRB’s) in a production environment to determine root cause of failures so that production line meets contractual requirements• Provide on-boarding to newly hired engineers to ensure assimilation with Lockheed Martin FPGA design and verification process

Responsible for the electrical design of Circuit Card Assemblies from concept to productionPerform schematic capture utilizing Cadence design toolsAssist layout personnel in the PWB development processDevelop firmware targeting Xilinx Virtex-6 and Spartan-6, and Altera Stratix-IV FPGA’s utilizing VHDLDevelop VHDL Test Benches for verification of firmware designsUtilize Xilinx ML605 Development board for FPGA prototyping, including the use of Serial RapidIO (SRIO) for inter-FPGA communicationExperience with Anti-Tamper (AT) designs and FPGA Design Security

Experience in firmware development of ATCRBS systems: Transponders, and InterrogatorsFamiliar with the operation of Mark XII IFF, including Mode 5, and Mode S.Experience with firmware development of ARINC 429 interfacesExperience with 802.11a/g wireless protocol firmware development and testing via MATLABDesigned, tested, and validated firmware for Identification, Friend or Foe (IFF) Systems, which utilize DPSK, MSK, and DSSS waveformsTested and validated 802.11a/g wireless IP core, including cross simulation between ModelSim and Matlab to verify resultsProgramed and configured Xilinx Virtex, Virtex-II, and Virtex-IV FPGA’s Utilized Chipscope via JTAG in conjunction with IFR test sets to debug firmware problemsOperate IFR test sets to verify proper IFF transponder and interrogator performance in accordance with AIMS specifications, and acceptance test procedures (ATPs)Designed cable and wire assemblies and provide flight test instrumentation support (temperature, vibration sensors) for Hyperspectral Imaging & Reconnaissance SystemsAssisted in the design of an RF Panel Test Fixture, which incorporated the use of RF Switches, Step Attenuators, RF Coupler, and RF CombinersSuccessfully participated in program design reviews with customers in support of the CMMI process. Experience with SRR, PDR, and CDR design review process and presenting to customer

Supervised a movement control team (MCT) operating out of KAF (Kandahar Airfield), Afghanistan during May 2004 - May 2005. Responsible for the coordination of all movement logistics throughout Kandahar, to include air shipments on C-130's, C-17's, personnel air transportation, and surface shipments via ground assets. Monitored and operated a quarterly budget of $15million for surface logistics.Developed custom macro-based Excel TCN generation system to reduce human error in shipments.

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