Digital IP design specialized in image processing: Camera sensor controller, LCD Controller, 2D-GPU, MIPI CSI2, MIPI DSI, MIPI DPHY.RTL/Gate simulation, synthesis, Clock-Domain Crossing (cdc), Reset Domain Crossing, formal proof analysis, timing analysis and optimization, power analysis and optimization.Semiconductor IC and IP Development according to ISO26262

Atos 5G Expert community member #AECTelecom : Technology monitoring, 5G URLLC presentation during Atos Expert Community Convention 2018 in MadridELINT signal processing: Architecture definition and development costing.Wide band demodulation system: FPGA developments on Intel FPGA Stratix10 device. Advanced timing analysis regarding hyper-retiming, hyper-pipelining, short path / long path, etc.... Adaptive digital signal processing modules. Validation team leader.

FPGA architecture and development of Layer1 4G LTE. Fixed-point bit-true modelisation in Matlab. System integration.Project management with deported team of 6 people: customer relationship, billing, FAT, schedule management. Budget 1M€-2M€.

FPGA development of Layer 1 cellular telecommunication (2G/3G). Fixed point bit-true modelisation in Matlab / C++. System integration.Blind digital demodulation system: FPGA developments of adptive signal processing modules, digital filtering and channelization.

Digital radio broadcasting repeater: FPGA developpment in VHDL. Bit stream data processing with turbo code, interleaving, OFDM modulation, DVB multiplex supervisor system: DSP development in C langage. Realtime processing of DVB data stream regarding ETSI TR 101 290 standard.

Adaptive digital predistorsion applied on power HF amplifier: Matlab simulations, LMS algorithms, radiofrequence measurement and qualification.