Anthony Cabrera Email & Phone Number

Mountain View, CA, US

Sunnyvale, CA, US

SoC Level Verification

Santa Clara, California, US

SSD Controller Design and Verification - SATA/PCIE Interface - DDR/SPI/NAND controllers- FW/HW Interface and driver development

Boise, Idaho, US

Design Validation and Silicon Bring-up LeadWear Leveling Algorithm and reliability improvement algorithm owner for MemoriesNOR and NAND Flash Memory firmware algorithmPre-silicon full chip verilog validation leadRTL and custom logic power analysis and improvement

Lead project planning efforts for design and validation tasks for clients.Designed and implemented circuit design environment for automation of circuit design and validation tasks. Formulated validation plan for both pre- and post-silicon validation including test platforms needed.

Rolle, CH

• Project Lead/Section Lead
• Led project which pioneered implementation of first data processing algorithm that conforms to the recently released 45nm Flash Memory ECC-NOR standard specification.
• Logic Section Circuit Design Lead for the following products Axcell Parallel NOR Flash Memory (512M) Axcell Parallel NOR Flash Memory (1G)____________________________________________________________Lead Circuit.
• Enable innovative circuit and software features based on marketing requirements
• Designed and implemented on-chip security features on a lead vehicle chip (NumonyxAxcell) http://www.numonyx.com/en-US/MemoryProducts/NOR/Pages/NumonyxIndustryStandardFlashM29.aspx (Numonyx Axcell Security features).
• Lead cross-site (Shanghai, California, Italy, Israel) and cross-functional (Sort, Class, SV, PVC, Q&R) task forces and validation teams

Santa Clara, California, US

• Project Lead/Design Validation Lead
• Led project which pioneered implementation of first data processing algorithm that conforms to the recently released 45nm Flash Memory ECC-NOR standard specification.
• Project Lead Logic Section Circuit Design Lead for the multiple flash memory densities StrataFlash Embedded Memory P30-130nm 256M StrataFlash Embedded Memory P30-130nm 256M (3% optical shrink) StrataFlash Embedded.
• Design Validation Lead Logic Section Circuit Design Lead for the following products StrataFlash Wireless Memory L18-65nm 256M ____________________________________________________________New Features Architect
• Define patentable circuit architectures and implement corresponding circuits. Enable innovative circuit and software features based on marketing requirements
• Circuit architect for boot load architecture and input decoding.

• Design block diagram level and VHDL/Verilog implementation of Universal Asynchronous Receiver/Transmitter, Instruction Cache and Data Cache modules
• Verification of implemented modules on Xilinx Virtex FPGA Test board.
• Design and Testing of CPLD/FPGA Boards (Spartan II FPGA (XC2S15)/ CoolRunner CPLD (XCR3032XL)/ XC9500 CPLD (XC9536XL))

US

• Implementation of a Network Element Management System (NEMS) using different J2EE networking technologies (RMI, CORBA, JMS, etc.)
• Implemented NEMS client using low level TCP/IP protocol with command parsing and interpretation

Ms-Ece, Microelectronics

Bs Physics, Physics