Anthony Cabrera Email and Phone Number
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Senior Circuit Design Engineer with 20 years experience from project conceptualization, architecture/circuit design, pre- and post-silicon validation to qualification and customer support. Very well-rounded in both digital/analog design and verification methodologies.Areas of expertise include:• Project/Team/Task Force leadership of cross-site teams with different functions (wafer/package testing, functional and performance characterization, reliability and yield improvement, test time reduction) • SystemVerilog and OVM/UVM verification• Firmware/microcode development in C or assembly for Flash memory algorithms (program, erase, reliability) • Fullchip/system architecture design interfacing between digital (HDL) and analog (full-custom) cells • Functional modeling • Post-silicon test methodologies including test definition, technical debugging, and microprobing Enjoys opportunities where major tasks have a direct impact on the enhancement on the company's bottom line and competitiveness.Specialties: Project/Task Force Leadership (Cross-site and cross-functional), Technical Debugging (Root Cause Analysis, Issue Resolution, Fix Definition), System Level Architecture/Circuit Design, Digital Design Entry (HDL)/Mixed-Signal Full-Custom Design entry, OVM/UVM /SystemVerilog. Firmware Development, Pre-Silicon Validation (Speed Path Modeling/Fullchip Functional Modeling), Software (Java/C++/perl/assembly,tcl)
- Website:
- google.com
- Employees:
- 1
- Company phone:
- 916.253.7820
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Application Specific Integrated Circuit Verification EngineerGoogle Apr 2022 - PresentMountain View, Ca, Us
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Senior Soc Design Verification EngineerAmazon Lab126 Mar 2021 - Mar 2022Sunnyvale, Ca, UsSoC Level Verification -
Soc Design And Verification EngineerIntel Corporation Feb 2017 - Mar 2021Santa Clara, California, UsSSD Controller Design and Verification - SATA/PCIE Interface - DDR/SPI/NAND controllers- FW/HW Interface and driver development -
Staff Design EngineerMicron Technology Apr 2011 - Feb 2017Boise, Idaho, UsDesign Validation and Silicon Bring-up LeadWear Leveling Algorithm and reliability improvement algorithm owner for MemoriesNOR and NAND Flash Memory firmware algorithmPre-silicon full chip verilog validation leadRTL and custom logic power analysis and improvement -
Founding Member - Staff Ic Design EngineerXinyx Design Jan 2010 - Dec 2010Lead project planning efforts for design and validation tasks for clients.Designed and implemented circuit design environment for automation of circuit design and validation tasks. Formulated validation plan for both pre- and post-silicon validation including test platforms needed.
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Senior Component Design EngineerNumonyx 2008 - May 2009Rolle, ChProject Lead/Section Lead • Led project which pioneered implementation of first data processing algorithm that conforms to the recently released 45nm Flash Memory ECC-NOR standard specification. • Logic Section Circuit Design Lead for the following products Axcell Parallel NOR Flash Memory (512M) Axcell Parallel NOR Flash Memory (1G)____________________________________________________________Lead Circuit Architect for Security Features • Enable innovative circuit and software features based on marketing requirements• Designed and implemented on-chip security features on a lead vehicle chip (NumonyxAxcell) http://www.numonyx.com/en-US/MemoryProducts/NOR/Pages/NumonyxIndustryStandardFlashM29.aspx (Numonyx Axcell Security features) http://www.numonyx.com/en-US/MemoryProducts/securityfeatures/Pages/default.aspx____________________________________________________________High Volume Manufacturing (HVM) Validation and Task Force Lead • Lead cross-site (Shanghai, California, Italy, Israel) and cross-functional (Sort, Class, SV, PVC, Q&R) task forces and validation teams• Prevented non-qualification of Numonyx products on major customer platforms by leading task forces to find the root cause of customer returns• Drives resolution to customer issues through circuit analysis and edit validation -
Senior Component Design EngineerIntel Apr 2004 - Apr 2008Santa Clara, California, UsProject Lead/Design Validation Lead • Led project which pioneered implementation of first data processing algorithm that conforms to the recently released 45nm Flash Memory ECC-NOR standard specification. • Project Lead Logic Section Circuit Design Lead for the multiple flash memory densities StrataFlash Embedded Memory P30-130nm 256M StrataFlash Embedded Memory P30-130nm 256M (3% optical shrink) StrataFlash Embedded Memory P33-130nm 256M (Password Protect Mode)• Design Validation Lead Logic Section Circuit Design Lead for the following products StrataFlash Wireless Memory L18-65nm 256M ____________________________________________________________New Features Architect • Define patentable circuit architectures and implement corresponding circuits. Enable innovative circuit and software features based on marketing requirements• Circuit architect for boot load architecture and input decoding.• Enabled permanent block locking feature and its proliferations ____________________________________________________________Test Time/Reduction Yield Improvement Lead • Saved the company more than $15 million through circuit and methodology changes for test time and yield improvement • Lead cross-site (Shanghai, California, Israel) and cross-functional (Sort, Class, SV, PVC, Q&R) to validate changes
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Digital Design/Test Engineer - Science Research Specialist IiAdvanced Science And Technology Institute Feb 2003 - Apr 2004• Design block diagram level and VHDL/Verilog implementation of Universal Asynchronous Receiver/Transmitter, Instruction Cache and Data Cache modules • Verification of implemented modules on Xilinx Virtex FPGA Test board.• Design and Testing of CPLD/FPGA Boards (Spartan II FPGA (XC2S15)/ CoolRunner CPLD (XCR3032XL)/ XC9500 CPLD (XC9536XL)) -
Software Design EngineerNec Telecom Software May 2001 - Jun 2002Us• Implementation of a Network Element Management System (NEMS) using different J2EE networking technologies (RMI, CORBA, JMS, etc.)• Implemented NEMS client using low level TCP/IP protocol with command parsing and interpretation
Anthony Cabrera Skills
Anthony Cabrera Education Details
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De La Salle UniversityMicroelectronics -
Ateneo De Manila UniversityPhysics
Frequently Asked Questions about Anthony Cabrera
What company does Anthony Cabrera work for?
Anthony Cabrera works for Google
What is Anthony Cabrera's role at the current company?
Anthony Cabrera's current role is Senior ASIC Design Verification Engineer at Google.
What is Anthony Cabrera's email address?
Anthony Cabrera's email address is an****@****126.com
What is Anthony Cabrera's direct phone number?
Anthony Cabrera's direct phone number is +120836*****
What schools did Anthony Cabrera attend?
Anthony Cabrera attended De La Salle University, Ateneo De Manila University.
What skills is Anthony Cabrera known for?
Anthony Cabrera has skills like Debugging, Tcl, Ic, Flash Memory, Vhdl, Semiconductors, Fpga, Asic, System Verilog, Firmware, Microcode, Verilog.
Who are Anthony Cabrera's colleagues?
Anthony Cabrera's colleagues are Jagadesh S, I Gede Ergi Ama, Puneet Garg, Pmp, Csm, Duc Nguyen, Lloyd Garmadon, Dongxia Liu, Ananya Choudhary.
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