Anthony Sixta Email & Phone Number

Mougins

Working on image processing system dataflow and architecture. We locally deal with picture quality (dxomark.com) and ISP system performance. In charge of all infrastructure IPs which allow debug capabilities, module configuration, interrupt, DMA and many more. We can implement HW, starting from C-code to RTL, through functional specification writing, systemC modeling, Low-level C-code optimization. I also used to spend time on helping on design/verification development, FPGA debug/analysis and backend issues.

Nice Area, France

Responsible for technical development, synthesis, schedule and SOC deliveries for the PCI-USB sub-system which consisted of USB 3.0 OTG DRD and PCI express Gen 3 controllers and PHYs.The IP is 5 mm2 in 28nm (200K flops) including 3 PLL, 8 complexIOs, ESD cells, 4 CMOS pads, 40 memories and is close DFT (stand-alone DFT IP).8 person local and remote team performing all tasks : including specification, IP/system integration, RTL coding, DFT, synthesis, STA, Backend, IrDrop, ESD, DV (RTL/Gate).A part of the sub-system has also been delivered to other programs for automotive market.Personally responsible for :• resolving technical issues (constraints, clock tree spec, balancing, IrDrop, power/voltage domain isolations, Gate Level Simulation debug …)• driving the team to synchronize all tasks• providing flows/checks for the deliveries to the SOC • performing synthesis for the complete design• writing/debugging STA constraints• Gate level debug with and without timing information

Nice Area, France

At the same time as IP developper and IP technical lead, the technical officer role is providing support for all following items:- Specification: validation, design, integration, functionalDFT: TDL, ATPG grading, TFT, IDDQ, Fastscan/Tetramax- Guidelines: design requirements, design improvements, methodology- Work closely with chip level to define IP design methodology- Improve PPA for all IPs by using design rules- Work with design zones, evaluate external IPs and reuse existing TI modules- Provide advanced ipgenerics/ipsynchro modules for a high IP design quality- Provide a technical support for all soft-macro and hard-macro IPs.- Delivery system: Soft macro and Hard macro, TI and non-TI- Design: RTL description, good practice, best implementation, bus interface- STA: OCV, AOCV, Xtalk, margins- Backend: IRdrop, power 5000x implementation, Always-on, Soft-Macro RAMs- Contacts: RAM models, new cells, EDA team, customer, NDA, DSUA…This activity leads to more than 20 tools used.

Nice Area, France

The USB synopsys IP has been hardened for several programs (Wireless, Automotive and Camera markets). Personally responsible for :• The RTL quality: new RTL code, Spyglass checks, power analysis, Equivalence check• The delivery dates and package content (RTL, Gate, Backend models, DFT, Timing Model)• STA constraints for all modes• Interface to SOC team for any issue (timing, Gate Level, DFT exceptions, …)• ECO implementation• Automatic generation of the integration and test plan specifications• Ensure convergence in the Timing signoff flow (Primetime debug)• Provide a Hard Macro flow for several IPs: LLI, EMIF, USB to ensure coherency between IPs

Nice Area, France

The HDMI Silicon Image IP has been provided as a Soft-Macro to OMAP3 (Wireless)Personally responsible for :• Project lead : driving the team and interfacing with the SOC team located in India• Helping to the functional specification : tradeoff between analog and digital worlds, debug capability, API definition• The RTL quality/deliveries: RTL code, Spyglass checks, power analysis, Equivalence check• RTL : clock/reset trees and Video Frame generation• Synthesis run and STA constraints for all modes• ECO implementation based on discussions with the 3rd party provider• Auto-generation of the registers/memory accesses based on the functional specification. The same generator has been re-used by several IPs.

Nice Area, France

The DigRF IP intends to connect to an Infineon Modem and has been created from the beginning based on discussion with Motorola. Personally responsible for :• Project lead : driving the design and verification team, responsible for the deliveries and dates• Responsible for the functional, integration and design specifications• RTL code• Mentoring designers on RTL, synthesis and power aspects • Reviewer of validation plan, test plan

Nice Area, France

The ISP block is the result of collaboration between Dallas, Tokyo and Nice teams. I was responsible for the Hardening of the IP (close DFT).Personally responsible for :• Project lead : driving the design and verification team, responsible for the deliveries and dates• RTL code for the integration of the different sub-blocks• Complex clock and reset tree was simplified to ease different tasks• synthesis and STA constraints and run • Reviewer of validation plan, test plan

Nice Area, France

I worked on different Camera receiver soft-macros versions (connected to sensors), always starting from a functional spec and the design was created from the beginning (CCP2 and parallel interfaces)Personally responsible for :• Driving the verification team and lead the development• RTL code (aligned with functional specifications)• Multi clock/reset trees • synthesis constraints and run

Nice Area, France

Continuity of the Sub-contractor mission through Altran Technologies.The IP has been used many years on different programs and TI has invested into USB 3rd party IPs since 2007.

Nice Area, France

In charge of the USB project (4 people), deliveries, support, development of an enhanced USB (USB Client and then On-The-Go) module for mobile phone. RTL development (VHDL), test, validation of the RTL and gate levels with modelsim and specman and software/customer support. We also had to comply with the compliancy testing.

Grenoble Area, France

Microboard Debug for atomic central: Hardware card debug using FPGA.

Education record

1 year spent in Motorola Toulouse (France) 3 months study in Madrid (Spain)

Math Sup - Math Spé M, Mathematics / Physics