Anup Das's Location
Philadelphia, Pennsylvania, United States, United States
Anup Das's Contact Details
Anup Das work email
- Valid
- Valid
Anup Das personal email
n/a
Anup Das phone numbers
About Anup Das
Anup Das is a Associate Professor at Drexel University. He is proficient in English.
Anup Das Work Experience Details
-
Associate ProfessorDrexel UniversityPhiladelphia, Pa, Us -
Associate ProfessorDrexel University Sep 2022 - PresentPhiladelphia, Pennsylvania, United States
-
Assistant ProfessorDrexel University Jan 2018 - Aug 2022Philadelphia, Usa
-
R&D EngineerImec Nov 2015 - Jul 2017Eindhoven Area, NetherlandsNeuromorphic Computing; Infrastructure for IoT -
Research FellowArm-Ecs Center, University Of Southampton Oct 2014 - Oct 2015Southampton, United KingdomI have worked on developing run-time managers as part of the Linux kernel to manage power and reliability of multicore embedded systems. -
Senior Research AssistantArm-Ecs Center, University Of Southampton Jun 2014 - Sep 2014Southampton, United Kingdom I have developed a run-time manager as a part of the operating system using model-free reinforcement learning algorithm. The proposed approach overrides operating system decisions to control the threads allocation on the CPU cores to minimize thermal emergencies (peak temperature, average temperature and also thermal cycles). Power reduction is achieved by switching the frequency of the processing cores dynamically during program execution, exploiting the chip-wide DVFS control knob. The run-time manager is developed for Linux operating system running on Texas Instument’s PandaBoard SoC (featuring dual-core ARM), Samsung Exynos5 SoC (featuring quad-core ARM big.LITTLE), quad-core Intel IvyBridge Processor and octa-core Intel Xeon Phi.
-
Research ScholarNational University Of Singapore Jul 2011 - May 2014SingaporeI am working on the developing a design-time methodology for the design of reliable multiprocessor system. There are two research directions. First, a design-flow is proposed to determine the number of cores and the size of FPGA fabric of a reconfigurable multiprocessor system which maximizes the reliability while satisfying the area, power and performance requirement. The proposed approach considers multiple concurrent applications, typical of modern multimedia systems. Then a task mapping technique is proposed to maximize the lifetime reliability of the overall system considering data, task and temporal parallelism. This technique also incorporates the lifetime reliability of underlying networks-on-chip. -
Visiting ResearcherArm-Ecs Centre, University Of Southampton Aug 2013 - Jan 2014Southampton, United KingdomI worked as a part of the PRiME project on intelligent algorithms for reliability and power optimisation. On the reliability front, I investigated on an adaptive approach which controls the mapping and scheduling of multimedia applications and the voltage and frequency of cores to control the peak and average temperature. The objective is to extend the system lifetime measured as mean‐time‐to‐failure (MTTF). On the power front, I also looked into online adaptations for power management using machine learning principles.
-
Visiting Research ScholarPolitecnico Di Milano May 2013 - Jul 2013Milan Area, ItalyI worked on self‐aware computing project at Politecnico di Milano for online management of performance, energy and reliability. A dynamic engine is developed based on observe‐decide‐act philosophy to control the thermal aging of cores by dynamically controlling the mapping of applications on many‐core architecture. Furthermore, communication energy is also minimized in the approach. -
Resaerch AssociateUniversity Of Massachusetts Amherst Jan 2010 - Jul 2011Springfield, Massachusetts AreaInvestigated on heterogeneous core fusion for performance improvement of multi-core systems. -
Senior Design EngineerLsi, An Avago Technologies Company Jan 2008 - Jul 2011RTL designer for Read-Channel IP of storage peripheral systems. DFT engineer for 1.5 Million gates flash system-on-chips with multi-power domains. Lead the low power scan related activities for million gates system-on-chip design. This included strategies for scan codec insertion for different power domains with a hand shaking of signals crossing domains. -
MtsTranswitch Aug 2007 - Jan 2008New Delhi, IndiaRTL designer for ethernet packet processor. -
Design Engineer IiStmicroelectronics Jul 2004 - Aug 2007Front end design engineer for audio and video peripheral IPs such as PCM Player, SPDIF Player and HDMI. Responsible for rtl design, synthesis, timing closure and DFT of individual IPs.
Anup Das Education Details
-
Embedded Systems
-
Electrical, Electronics And Communications Engineering
Frequently Asked Questions about Anup Das
What company does Anup Das work for?
Anup Das works for Drexel University
What is Anup Das's role at the current company?
Anup Das's current role is Associate Professor.
What is Anup Das's email address?
Anup Das's email address is an****@****xel.edu
What is Anup Das's direct phone number?
Anup Das's direct phone number is +316386*****
What schools did Anup Das attend?
Anup Das attended National University Of Singapore, Jadavpur University.
Not the Anup Das you were looking for?
-
5gmail.com, gmail.com, virtusa.com, virtusa.com, virtusa.com
-
2sap.com, yahoo.com
-
1gmail.com
Free Chrome Extension
Find emails, phones & company data instantly
Find verified emails from LinkedIn profiles
Get direct phone numbers & mobile contacts
Access company data & employee information
Works directly on LinkedIn - no copy/paste needed
Aero Online
Your AI prospecting assistant
Select data to include:
Total price:
$0.00
0 records × $0.02 per record
Download 750 million emails and 100 million phone numbers
Access emails and phone numbers of over 750 million business users. Instantly download verified profiles using 20+ filters, including location, job title, company, function, and industry.
Start your free trial