Anup Kini Email & Phone Number

Opfikon, Zh, Ch

Zurich, Switzerland

Bengaluru Area, India

Gluon @ TSMC 16nm, MPW Shuttle Feb 2021- Worked on design, RTL, module level verification, power optimisation, synthesis & GLS.- Worked on config & interfacing JTAG debugger, PCIe Gen3 X16 & LPDDR4 IP- Gluon Tapeout Lead – responsible for all releases from RTL team, point-of-contact for external IPs, DFT, PD and Packaging team.- Worked with PCB design vendor on design of bring-up board and post-silicon validation.- Design of RAP Agent with FP32 compute modules for Edge Learning (Zero Shot learning)- Prototyping RAP on AlphaData VU37P & Xilinx VCU1525 and optimizing the design for freq, area & power for various Edge Learning workloads -AlphaEdge (ZYNQ + 2xVU9P) & AlphaDrive (ZYNQ + 2xVU9P) - worked on ZYNQ block design, PL based PCIe RC, Interlaken links between VU9P, PetaLinux/Yocto image- Awarded Star of Year 2018 for Excellence in VLSI Design (Dec 2018)

Bengaluru Area, India

- Multi-FPGA implementation of 256 node REDEFINE, using proFPGA and Xilinx Vivado tools and manual IP planning across 6 FPGAs. This work has been presented at Hello Tomorrow 2016 at Paris and 4th RISC-V Conference held at MIT- Prototyped REDEFINE accelerator on multiple Virtex-7 FPGA boards interconnected to Microblaze as the host processor and DDR3 as shared memory. We were able to issue multiple kernel requests from user applications running on Linux. Currently, extending this towards RISC-V based lowRISC processor - Team Member in developing a scalable, mesh toroidal Network-On-Chip, to be used as interconnect within REDEFINE. The design is routing and message dependent deadlock free- Team Member in developing a 32-bit 5-stage pipeline processor for extended RISC-V ISA, to be used as processor core in REDEFINE. Control and Data hazards were handled in the processor design. Other features were operand forwarding and interface with the hardware distributed run-time- Developed a Single Precision Floating-point Unit (Add/Sub, Multiply, FMA, Conversion) in Chisel HDL, based on RISC-V ISA, as a custom functional unit for REDEFINE- Team Member in design and development of a post-silicon reconfigurable vector processing datapath. This module adds as a custom functional unit in REDEFINE- Developed AXI compatible Hardware Global Resource Manager, a bridge between the Host and the REDEFINE accelerator. It keeps track of status of execution resources, maps the kernels to execution resources, compute and fill page tables and configure the hardware run-time with kernel metadata- Design and implementation of OpenCL like user space device driver for REDEFINE, to be used as a custom accelerator with any Linux based Host processor like Microblaze, RISC-V based lowRISC

Gruibingen, Germany

- Design, Implementation and Testing of Partial Reconfiguration Engine on custom ZYNQ platform.- Design of hardware accelerator modules on the FPGA to process USB driven Kinect Sensor.- Enabling User IO access from Linux user-space for hardware modules on FPGA.- Implementation of image processing kernels for 3D image processing using Xilinx OpenCL.- Customization of Real-Time OS Xenomai and user space to ZYNQ custom board.- Board bring-up and testing of U-Boot, Linux kernel and Yocto/Open-Embedded based file-system for ZYNQ, SnapDragon 800, iMX-6 and NVidia T30.- Design and testing of U-boot based network access stack (TCP/IP), upgraded to WebSockets to communicate to a server.

Bengaluru Area, India

- Developed customised banking menus using HTML, J2EE, C/C++ and SQL.- Worked for maintenance and support team, providing patches for live-customer bugs.- FINACLE On The Spot Award – for exceptional development skills and on time.