Aravind Chandramohan Email & Phone Number

Cupertino, California, Us

Austin, Texas, Us

o Hierarchical block implementation (chipset) at 16nm from synthesis to gds including floorplanning, IO pin placement and budgeting, formal verification, static timing analysis, drc closure, constraints writing, timing/functional ECO implementation and power analysis.o Flow development activities – clock tree, AOCV analysis, signalEM analysis and power reduction techniques.o Timing closure (STA) across DVFS/MCMM scenarios using manual and dmsa techniques.o Power Analysis in Redhawk including setup, apl model generation using apldi hspice simulation.o Block build for ARM processor with L2 caches.

Palo Alto, California, Us

Redhawk analysis for Static – IR, power EM, signal EM, Dynamic and Rampup Analysis and Scan Shift high power state.Block hardening from rtl to gds for complex SerDes and high frequency blocks.28nm flow development for PnR and Power analysis.

Dallas, Tx, Us

SoC for world satellite radio application (Tensilica Core)o Own all Physical Design activities for block and top levelo Staggered inline IO placement at top levelo Perform full chip layout activities including floorplanning, physical partitioning, placement, clock tree synthesis, routing, timing closure and physical verification.o Project Scheduling, performed risk identification and mitigation planning.

Bangalore, Karnataka, In

Complex Low-power SoC for automotive safety and catalog market (dual core CortexR5 implementation), multi-vt, multi-library, multi-voltage.o Full chip IO placement, sub-chip and top level floorplanningo Power estimation and implementationo Charged with physical design spec ownership, project scheduling and tracking including complex IO developmento Completed sub-chip partitioning based on power and voltage domains, timing criticalities, and safety requirementso Risk identification and mitigation plans including mentoring junior team members

Dallas, Tx, Us

Tool evaluation including full design flow for QoR including performance, power, area, timing correlation, runtimes and flow development; Multi-Mode, Multi-Corner, 65nmo ICC, Synopsyso Talus Flow Manager (TFM) by Magmao Spyglass Physical, Atrenta for architectural evaluation and early prototypingo Redundant Via ImprovementsPhysical design for complex Soc for video based application (40nm)o Performed IR drop analysis using Redhawk (Apache) and Quartzrail (Magma) toolso Physical verificationDeveloped QC checkers using Tcl and Perl scriptingAttended Cadence Encounter training

Bangalore, Karnataka, In

o Performed top level IO placement, floorplanning; ARC closure for QFP package and analog routingo Placement, CTS, route, DRC closure, extraction and timing closureo Power planning, power grid implementation and IR analysiso Physical verification (SI, EM, DRC, LVS,) and ESD checkso Mentored junior team memberso Metal level Eco (functional and timing) implementation and Netlist Eco flow

Bangalore, Karnataka, In

o Developed test plans and assembly level test caseso Test pattern identification and generation for characterization and productiono RTL and netlist simulations for VCD generations

Certification, Dsp For Identification And Control

Certification, Electronic Design

B.E., Electrical And Electronics