Arie Margulis Email and Phone Number

Manager and technical lead of a group of 25 engineers working on DFX design, verification, scan and ATPG of state of the art AMD dGPU SoC.

- Leading four engineers DFT Group responsible for DFT of three ASIC designs simultaneously.- Working in collaboration with different Freescale design centers all over the world, including Europe, US, India and China design centers.- Defined Scan Methodology and Architecture, including Last-Shift transition scan method, and TestKompress compression method, of Dual Core and Single Core, multi-Clock-Domain and multi-Scan-Domain SOCs with more then 200K FFs. The methodology and architecture was adopted in various Freescale design centers all over the world.- Defined PLL Chopper solutions for Broadside and Last-Shift Transition Scan Implementation.- Developed security solutions and architecture for DFT modes.- Defined Memory-BIST solutions.- Developed scripts for quick failure-analysis of scan failures on silicon.- Performed ATPG tools benchmarks.

- Performed Top-Level STA checks for multi clock domain SOCs using ETM and QTM timing models and Synopsis Primetime tool.- Performed Timing Constraints budgeting and STA checks for multi clock domain MIX blocks.- Carried-out evaluation of the results correlation betwee Cadence First-Encounter and Synopsis Primetime STA tools in cooperation with Cadence design center in France.

- Implemented Scan Architecture of Dual-Core and Single-Core, multi-Clock-Domain and multi-Scan-Domain SOCs with more then 200K FFs.- Performed Generation of Stuck-At, Transition and Path-Delay scan-patterns using Mentor Fastscan and TestKompress tools.- Increased Scan coverage of ASIC design by solving various testability problems, implementing test wrappers and Ram ATPG solutions.- Performed Simulation and Debug of scan-patterns in Wgl and Verilog formats.- Developed scripts for scan-insertion stage of Physical-Compile Synopsis synthesis tool- Provided support to a team of Test-engineers on conversion of Wgl scan-patterns into tester format, and on debugging the failures of scan-patterns on silicon.- Implemented internal and external vendor Memory-BIST solutions for Kilobit and Megabit embedded repairable RAMs.- Implemented Jtag and Boundary-Scan architecture.- Performed Evaluation of Cadence Encounter-Test ATPG solution.- Performed Generation of Stuck-At and Transition patterns using Synopsis TetraMax tool.

- Created and Debugged system verification tests for Verilog simulation environment.- Created and Debugged system verification tests for Evaluation-board environment.- Performed Chip Power consumption estimation using PrimePower Synopsis tool.

Tested and verified multimedia software solutions on various IBM-PC and Macintosh platforms.