Arijit Pramanik Email & Phone Number

Bengaluru, Ka, In

Bengaluru Area, India

As a Technical Lead and Manager in Platform Functional Modelling Team delivering high quality Virtual Platforms to accelerate Pre-Silicon validation.Working extensively on Power Management IPs and other Boot Critical IPs such as SPI, eSPI, NVMe, SATA etc. for System FW/SW/Driver/BIOS Development and Validation.This work also includes System FW Integration and enabling of Boot, Reset and other Advanced PM flows such as Modern Standby for Laptop and Discrete Graphics products.

Bengaluru Area, India

As a Technical Lead, assumed Product Ownership of Graphics Debugger for its development and support activities across all Graphics products in Integrated and Discrete space. This supports all available pre & post silicon GPU target types and is heavily used by all Internal & External stakeholders for development and debug activities.These efforts also include the following,• Implementation of Scheduler & Instruction Buffer decode with replay. • Implementation of all available Graphics Memory Translation Page-Walks to read System & Discrete Graphics memory accurately. • Implementation of 3D pipeline State Recorder. • Implementation of Shader instruction decode and analysis.

Bengaluru Area, India

As an individual contributor, developed and supported Silicon Validation Test Loader and Application interface to read & modify memory associated with Intel GPUs.This effort also includes the following,• Owning full responsibilities for 2 projects while closely supporting System Validation team including Power-On SW readiness to PRQ• Implementation of Graphics Scheduler Dispatch & Completion logic to run complicated cross platform test content. • Design & Implementation of HDCP2.2 Authentication protocol while establishing a new interface to communicate with Security Firmware.

Bengaluru Area, India

As an individual contributor, developed and deployed Intel's first automated debug solution for SoC & GPU post silicon failures. This development effort also includes,• Developing a new debug automation framework with signature-based failure bucketing and test minimization/debug experiment flows for both CPU & GPU to converge on debug methodologies.

Bengaluru Area, India

As an Intern in Intel's SOC validation team, implemented methodology to utilize a new Tracing Interface (PTI & STM) to get accurate performance metrics in SoC during Post Silicon Validation while capturing the time stamped transactions through buses and representing those in graphical format.

M.Tech, Computer Science

B.Tech, Computer Science