1. Started my work with GLS on Transition Fault patterns for both Zero-Delay and Timing.2. Worked on XLS based flow development for Scan Insertion on Synopsys FC.3. Working on scan insertion on various hard macros and subsystem levels and fixing issues related to tool limitation, design changes etc.4. Working on ATPG on subsystem level and retargetting.

1. Worked on ATPG to generate patterns using Mentor Graphics Tessent Testkompress. And simulate them on Cadence Incisive tool. 2. Automated a setup environment for regression which uses Cadence Xcelium to reduce compilation and elaboration time of netlist for every testbench simulation. Now only one compilation and elaboration of netlist is required and every testbench in regression uses the same database to simulate patterns. For setup and automation I used perl and shell scripting.3. Worked on Scan Insertion on Hard Macro level on Synopsys DC and enabled various features like Scan Compression, Test Point insertion, Core Wrapping etc.4. Enabled SHS based solution for running LBIST using in-house JTAG Machine.

Worked in DFT Team on LBIST and ATPG. 1. STUCKAT, ATSPEED and BurnIn pattern generations for SOC using Mentor Graphics Tessent TestKompress. Simulating Patterns using Cadence Incisive Enterprise Manager. Debugging SOC on circuit level.2. LBIST Simulation

I was Teaching Assistant for Embedded Logic Design during Aug, 2016 - Nov, 2016 and for Introduction to Engineering Design during Jan, 2017 - April, 2017.