Arjun Gill Email & Phone Number

Santa Clara, California, Us

- Server DFT Engineer, responsible for DFT efforts involving large scale server microprocessors. ATPG for Static/Timing/UDFM faults (Tessent), low coverage debug, RTL and Netlist feedback, pattern validation and simulation in both RTL and Netlist environment.- DFT Architecture, RTL verification of directed DFT tests covering test structures, clocking and constrain validation, RTL feedback and bug tracking.- Spyglass DFT, coverage, constrain, and RTL review/feedback.

San Diego, Ca, Us

- ATPG bring-up engineer, test pattern generation and silicon debug (TestKompress and TetraMAX). Bug tracking and drive of silicon issues to closure by working across multiple design and engineering teams.- Volume diagnostics and yield improvement. Interface across teams to generate the volume diagnostics database and help identify yield improvement avenues.- Test Time Reduction- Automation/Tools/Flow development: - Created push button flows for supplemental test vectors (Logic Retention, Characterization, and Burn-in) - Volume diagnostics tool development

College Station, Tx, Us

- Research methods to minimize system level test failures and Small Delay Defect fault escapes in production test. - Worked on enhancing an existing ATPG tool to generate multi-cycle long path delay tests.

Santa Clara, California, Us

- Developed a novel Small Delay Defect (SDD) Top-Off ATPG methodology that utilized existing Transition pattern set and generated Top-Off SDD patterns. The results were presented at the International Test Conference (2013).- Developed a holistic test pattern reduction methodology to work across Stuck-at, Transition, Cell Aware and Small Delay Defect pattern sets.

Dallas, Tx, Us

- Generation, validation and silicon bring-up for an MCM design; Stuck-at, Transition, IDDQ, Path Delay, Boundary Scan and MCM connectivity test vectors.- Integration, RTL development and validation of memory BIST, Scan Compression logic, DFT controller, Boundary Scan and JTAG for an ASIC.- Module level ATPG and top level memory BIST implementation of an SOC.- ATPG vector generation, validation and silicon bring-up for multiple ASICs.- Automation/Flow development----- DFT test clock controller verification flow which would program the test clock controller, simulate, parse the simulation dump (VCD) and check that correct test clocks were observed through the design.----- ATPG vector delivery flow which ensured that the delivered vectors from the DFT team to TEs did not contain any missing files. It would also parse the vectors to check for known issues which caused vector failure on the tester.

Dallas, Tx, Us

- Developed a flow which could get an early estimate of Scan Shift power using statistical analysis which did not require a vector simulation and power estimation based on simulation.- Helped complete the ongoing research on reducing Transition Fault Test power. The results were shared in IEEE Asian Test Symposium, November 2008.

Master Of Science (Ms), Computer Engineering

Bachelor Of Engineering (B.E.), Electrical And Electronics Engineering