• TPM driving MCP/SiP product development and qualifications for external customer from initial spec alignment to mass production (xVT builds to MP) by collaborating with cross-functional teams including circuit design and I/O, device, test, packaging, reliability, manufacturing, and supply chain. • Technical lead managing customer failure analysis activities ranging from wafer to system-level failures addressing early development phase builds failures and RMAs. • Drive product quality improvement via developing and implementing containment strategies for systematic failures and failures exceeding allowed DPPM level.• Reduced failure analysis turn-around-time by 40%

• Focused on Memory technologies (DRAM, 3D-DRAM, and 3D-NAND) to identify technology roadmap inflections and industry's strategic High Value Problems.• Demonstrated on wafer integration of innovative solutions for critical manufacturing challenges with emphasis on Ion Implant, Ion Beam, RIE, thin film deposition and material modification processes. • Developed optimized ion implantation process to improve device performance, yield, and reliability.

• Process Integration Pathfinding:o Led cross-functional teams to define and establish memory product roadmap (Planar DRAM, 3D-DRAM and 3D-NAND). o Defined critical structural specs based on the interaction of involved processes variations (Advanced JMP analysis) o Identified process integration roadblocks and led internal teams along with external vendors to resolve them.o Experienced in planar DRAM integration pathfinding with primary focus on: STI module (HAR Si etch and drying) | Wordline module (Alternative wordline metals integration, hybrid metal gate for GIDL control) | Bitline module (alternative Bitline metals integration and alternative low-k spacer schemes) | Capacitor module (Alternative high-k and drying)o Experienced in 3D-NAND integration pathfinding with primary focus on: Memory Hole Module (HAR etch profile, dual/triple deck integration schemes) | RMG module (Highly selective drying and wordline formation integration) | Bitline module (Integrated novel low RC Bitline module)o Part of initial 3D DRAM research group working on multiple architecture options and scaling scenarios• R&D Process Development:o Developed, qualified, and released wafer fabrication processes for metallic and dielectric CMP.o Improved process maturity by reducing process variations utilizing Six Sigma techniques and incorporating ML algorithms into process.o Experienced in manufacturing fab large process data analysis to improved product yield (advanced JMP).o Controlled and monitored processes (SPC) and transferred to oversees manufacturing (HVM) sites. o Defined critical structural specs based on the interaction of involved processes variations (Advanced JMP analysis) o Qualified and release first of a kind manufacturing tools and processes.o Developed advanced internal hardware capabilities to improve manufacturing process.o Developed advanced software tools to support engineering work in R&D and manufacturing for process development. (Using MATLAB)

• Developed a non-destructive ultrasonic-based vibrational spectroscopy method along with a mathematical model to characterize the surface energy of micro-scale particles and monolayer graphene• Developed a novel micro-particle transport/manipulate technique using surface acoustic waves along with a mathematical model for surface characterization• Developed a non-invasive technique using signal processing to extract geometricaland mechanical properties of soft materials• Designed and improved the response of MEMS capacitive microphones by cancelling mechanical and electrical shocks(Computational Study).• Studied the thermal stresses effects on the mechanics and stability of micro-structures by considering the coupling betweenthermal and elastic fields (Computational Study).• Studied the nonlinear dynamics of MEMS subjected to nonlinear external excitations (Computational Study).