Arpan Chakraborty Email and Phone Number
I graduated from Jadavpur University in Electronics & Tele-communication Engineering.During my Bachelor's I Interned at Texas Instruments ,SAMEER Kolkata Centre and skilled in Analog Design,Layout , RF design, PCB development, and problem-solving.My technical toolbox includes proficiency in C/C++, Python and various design software like LT Spice, Cadence Virtuoso ,Cadence Spectre, ADS HFSS and LabVIEW. I'm passionate about problem-solving and thrive in collaborative environments.Apart from that I am an avid learner of Geopolitics , Finance and Semiconductors for future . I also love to do Trading and use my profound knowledge in doing meticulous technical analysis for my sound trading strategies and better returns !!I would love to have talks on Servers ,Data centers, GPU that are evolving for the future .
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Analog Validation EngineerTexas Instruments Aug 2024 - PresentBengaluru, Karnataka, IndiaJoined the Department of Interface & Processor Power( Multiphase Controllers) as an Analog Validation Engineer.Responsible for Validation of Multiphase Controllers inclined to the Production line of delivering Power to servers, particularly in high-performance computing (HPC) environments,Cloud Computing, data centers, or high-end workstations.
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Undergraduate Engineering StudentJadavpur University Aug 2020 - Jul 2024Final Year Project - Design, Layout of an Ultra Low Noise LDO with a PSRR of -40dB within a Bandwidth of 1MHz range for Low power Applications. Tools and Technologies Used- 180nm TSMC Node, Cadence Virtuoso, Cadence Spectre, LTSpice -
Analog Validation Engineer InternTexas Instruments May 2023 - Jul 2023Bengaluru, Karnataka, IndiaI have done three Projects during my Internship Period in Linear Power ---->Voltage Reference and Supervisor team ( Analog Power Products Division). Details are as follows 1) Strain Sensitivity Analysis of PNP AND NPN Bipolars in Series Reference Test Chip.2) PCB Development of Buried Zener Based Shunt Voltage Reference Testchip. (Tapeout,Fabrication of PCB was also done during my Internship Period)3) A Novel Approach to design a Power Supply Noise Supressor Circuit with a PSRR of -40 dB within a Bandwidth of 0.1 Hz to 1MHz .
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Rf Design InternSameer (R&D Of Dit, Govt Of India) May 2022 - Jul 2022Kolkata, West Bengal, India•Design of a miniaturized Stepped Impedance RF lowpass filter with Open circuit Stubs at Cutoffaround 2.5 GHz.Tools & technologies used: Keysight ADS, HFSS.
Arpan Chakraborty Education Details
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Cgpa-8.96
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Atreyee Dav Public School(557/600) 92.83 ℅ -
Atreyee Dav Public SchoolCgpa 10
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The Atreyee English Medium School
Frequently Asked Questions about Arpan Chakraborty
What company does Arpan Chakraborty work for?
Arpan Chakraborty works for Texas Instruments
What is Arpan Chakraborty's role at the current company?
Arpan Chakraborty's current role is Analog Validation Engineer @Texas Instruments India || Undergrad @Jadavpur University || Former Analog Validation Intern @Texas Instruments || Former RF Design Intern @SAMEER kolkata centre.
What schools did Arpan Chakraborty attend?
Arpan Chakraborty attended Jadavpur University, Atreyee Dav Public School, Atreyee Dav Public School, The Atreyee English Medium School.
Who are Arpan Chakraborty's colleagues?
Arpan Chakraborty's colleagues are Ayush Modi, James Harris, Steve Shoener, Karen T. Cheng, Cpe, Lisa Barringer, Cassandra Dreher, Chandra Chooda.
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